Authors:
- Devoted to logic synthesis and optimization for Complex Programmable Logic Devices
- Presents logic synthesis and optimization methods dedicated for Programmable Array Logic –based structures
- Written by leading experts in the field
Part of the book series: Lecture Notes in Electrical Engineering (LNEE, volume 231)
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Table of contents (9 chapters)
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Front Matter
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Back Matter
About this book
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can also be interpreted as programmable AND-fixed OR structure, well known as PAL-based structure. The question is: what should be done when the number of implicants representing function exceeds the number of product terms available in a logic block. The answer is ... in the book.
Logic synthesis and optimization methods dedicated for PAL-based structures are proposed. The methods strive to find the optimum fit for the combinational logic and finite state machines to the structure of the logic device and aim at area and speed optimization. The theoretical background and complete strategies are richly illustrated with examples and figures.
Authors and Affiliations
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Institute of Electronics, Silesian University of Technology, Gliwice, Poland
Robert Czerwinski, Dariusz Kania
Bibliographic Information
Book Title: Finite State Machine Logic Synthesis for Complex Programmable Logic Devices
Authors: Robert Czerwinski, Dariusz Kania
Series Title: Lecture Notes in Electrical Engineering
DOI: https://doi.org/10.1007/978-3-642-36166-1
Publisher: Springer Berlin, Heidelberg
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer-Verlag Berlin Heidelberg 2013
Hardcover ISBN: 978-3-642-36165-4Published: 12 January 2013
Softcover ISBN: 978-3-642-44224-7Published: 25 June 2015
eBook ISBN: 978-3-642-36166-1Published: 12 January 2013
Series ISSN: 1876-1100
Series E-ISSN: 1876-1119
Edition Number: 1
Number of Pages: XV, 172
Topics: Circuits and Systems, Logic Design, Engineering Design