Skip to main content
SpringerLink
Log in

Pipelined Multiprocessor System-on-Chip for Multimedia

  • Book
  • © 2014

Overview

Authors:
  1. Haris Javaid

    1. School of Computer Science and Engineeri, University of New South Wales, Kensington, Australia

    View author publications

    You can also search for this author in PubMed   Google Scholar

  2. Sri Parameswaran

    1. School of Computer Science and Engineeri, University of New South Wales, Kensington, Australia

    View author publications

    You can also search for this author in PubMed   Google Scholar

  • Describes the state-of-the-art on pipeline-level parallelism and multimedia MPSoCs
  • Includes analytical models and estimation methods for performance estimation of pipelined MPSoCs
  • Covers several design space exploration techniques for pipelined MPSoCs
  • Introduces an adaptive pipelined MPSoC with run-time processor and power managers
  • Introduces Multi-mode pipelined MPSoCs for multiple applications

This is a preview of subscription content, log in via an institution to check access.

Access this book

Log in via an institution
eBook USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (9 chapters)

  1. Front Matter

    Pages i-viii
    Download chapter PDF

  2. Introduction

    • Haris Javaid, Sri Parameswaran
    Pages 1-20

  3. Literature Survey

    • Haris Javaid, Sri Parameswaran
    Pages 21-52

  4. Optimisation Framework

    • Haris Javaid, Sri Parameswaran
    Pages 53-64

  5. Performance Estimation of Pipelined MPSoCs

    • Haris Javaid, Sri Parameswaran
    Pages 65-83

  6. Design Space Exploration of Pipelined MPSoCs

    • Haris Javaid, Sri Parameswaran
    Pages 85-100

  7. Adaptive Pipelined MPSoCs

    • Haris Javaid, Sri Parameswaran
    Pages 101-126

  8. Power Management in Adaptive Pipelined MPSoCs

    • Haris Javaid, Sri Parameswaran
    Pages 127-145

  9. Multi-mode Pipelined MPSoCs

    • Haris Javaid, Sri Parameswaran
    Pages 147-162

  10. Conclusions and Future Work

    • Haris Javaid, Sri Parameswaran
    Pages 163-165

  11. Back Matter

    Pages 167-169
    Download chapter PDF
Back to top

Keywords

About this book

This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors’ combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.

Authors and Affiliations

  • School of Computer Science and Engineeri, University of New South Wales, Kensington, Australia

    Haris Javaid, Sri Parameswaran

Bibliographic Information

  • Book Title: Pipelined Multiprocessor System-on-Chip for Multimedia

  • Authors: Haris Javaid, Sri Parameswaran

  • DOI: https://doi.org/10.1007/978-3-319-01113-4

  • Publisher: Springer Cham

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer International Publishing Switzerland 2014

  • Hardcover ISBN: 978-3-319-01112-7Published: 09 December 2013

  • Softcover ISBN: 978-3-319-34711-0Published: 27 August 2016

  • eBook ISBN: 978-3-319-01113-4Published: 26 November 2013

  • Edition Number: 1

  • Number of Pages: VIII, 169

  • Number of Illustrations: 8 b/w illustrations, 32 illustrations in colour

  • Topics: Circuits and Systems, Processor Architectures, Electronics and Microelectronics, Instrumentation

Publish with us

Policies and ethics

Back to top

Search

Navigation