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Engineering - Circuits & Systems | Constraining Designs for Synthesis and Timing Analysis - A Practical Guide to Synopsys Design (Authors and Editors)

Constraining Designs for Synthesis and Timing Analysis

A Practical Guide to Synopsys Design Constraints (SDC)

Gangadharan, Sridhar, Churiwala, Sanjay

2013, XXVII, 226 p. 116 illus.

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Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, with two decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx.

Sridhar Gangadharan  is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass  RTL Analysis Products at Atrenta. He has over 20 years of experience in the electronic design automation industry. His interest areas include RTL verification, timing closure, delay calculation and memory compilers. He holds a Bachelors degree in Computer Science and Engineering from Indian Institute of Technology in Delhi. He is based in San Jose, CA.

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    Constraining Designs for Synthesis and Timing Analysis

    A Practical Guide to Synopsys Design Constraints (SDC)

    Gangadharan, Sridhar, Churiwala, Sanjay 2013

    Price from $89.95
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    $89.95 (net)
    ISBN 978-1-4614-3269-2
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