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UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs

  • Book
  • © 2013

Overview

Authors:
  1. Martin Daněk

    1. , Pod Vodárenskou věží 1143/4, ÚTIA AV ČR, v.v.i., Praha 8, Czech Republic

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  2. Leoš Kafka

    1. , Pod Vodárenskou věží 1143/4, ÚTIA AV ČR, v.v.i., Praha 8, Czech Republic

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  3. Lukáš Kohout

    1. , Pod Vodárenskou věží 1143/4, ÚTIA AV ČR, v.v.i., Praha 8, Czech Republic

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  4. Jaroslav Sýkora

    1. , Pod Vodárenskou věží 1143/4, ÚTIA AV ČR, v.v.i., Praha 8, Czech Republic

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  5. Roman Bartosinski

    1. , Pod Vodárenskou věží 1143/4, ÚTIA AV ČR, v.v.i., Praha 8, Czech Republic

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  • Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch
  • Provides VHDL sources for the described processor
  • Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines Includes programming by example in the micro-threaded assembly language
  • Includes supplementary material: sn.pub/extras

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Table of contents (9 chapters)

  1. Front Matter

    Pages i-xviii
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  2. Programming Interface

    1. Front Matter

      Pages 1-1
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    2. Introduction

      • Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 3-7

    3. The LEON3 Processor

      • Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 9-14

    4. Microthreaded Extensions

      • Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 15-43

    5. The Basic UTLEON3 Architecture

      • Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 45-66

    6. UTLEON3 Programming by Example

      • Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 67-77

  3. Implementation

    1. Front Matter

      Pages 79-79
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    2. UTLEON3 Implementation Details

      • Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 81-109

    3. Execution Efficiency of the Microthreaded Pipeline

      • Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 111-126

    4. Hardware Families of Threads

      • Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 127-158

    5. I/O and Interrupt Handling in the Microthreaded Mode

      • Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 159-172

  4. Back Matter

    Pages 173-219
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Keywords

About this book

This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs.

Authors and Affiliations

  • , Pod Vodárenskou věží 1143/4, ÚTIA AV ČR, v.v.i., Praha 8, Czech Republic

    Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosinski

Bibliographic Information

  • Book Title: UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs

  • Authors: Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosinski

  • DOI: https://doi.org/10.1007/978-1-4614-2410-9

  • Publisher: Springer New York, NY

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer Science+Business Media, LLC 2013

  • Hardcover ISBN: 978-1-4614-2409-3

  • Softcover ISBN: 978-1-4899-9570-4

  • eBook ISBN: 978-1-4614-2410-9

  • Edition Number: 1

  • Number of Pages: XVIII, 222

  • Topics: Circuits and Systems, Processor Architectures, Electronics and Microelectronics, Instrumentation

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