UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs
Daněk, M., Kafka, L., Kohout, L., Sýkora, J., Bartosiński, R.
2013, XVIII, 222 p.
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Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch
Provides VHDL sources for the described processor
Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines
Includes programming by example in the micro-threaded assembly language
This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs.
Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch;
Provides VHDL sources for the described processor;
Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines;
Includes programming by example in the micro-threaded assembly language.