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Engineering - Circuits & Systems | Low Power and Process Variation Aware SRAM and Cache Design

Low Power and Process Variation Aware SRAM and Cache Design

Sasan, Avesta, Kurdahi, Fadi, Eltawil, Ahmed

2015, 200 p. 100 illus.

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ISBN 978-1-4614-2272-3

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  • About this book

  • Describes a variety of design solutions for voltage scalable SRAM/Cache architectures with reliability tolerance to process variation
  • Explains cross layer voltage and power management, enabling system level awareness of manufacturing defects and circuit/architectural mitigation techniques
  • Includes techniques for building fault free system using faulty components/memories
  • Explores tradeoffs between power consumption, area, reliabality and performance in nano region memory design
This book addresses process variability and power management for embedded memories, which are becoming dominant components in today’s Systems on Chip (SoCs).  It provides thorough background on voltage scaling and the reliability effects on memories, while describing memory behavior at different voltages and frequencies. The authors describe a cross-layer approach, simultaneously targeting the manufacturing of devices, the inner-design of the memory circuits, as well as the way they are architected into a system.  This approach enables the design of reliable, power-efficient systems in which memories are dominating area, power, and performance.

Content Level » Research

Keywords » Embedded Memory Design - Fault tolerant memory design - Low power memory design - Memory Circuit Design - Process Variation Aware SRAM - SRAM design - System on Chip - Voltage scalable SRAM/Cache architectures

Related subjects » Circuits & Systems - Communication Networks - Electronics & Electrical Engineering

Table of contents 

Introduction.- SCPS Cache.- RDC-Cache.- IDC-Cache.- VTD-Cache.- Conclusions.

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