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Engineering - Circuits & Systems | SystemVerilog for Design and Verification using UVM - From RTL to Synthesis

SystemVerilog for Design and Verification using UVM

From RTL to Synthesis

Azadpour, Mark A.

2015, 300 p. 100 illus.

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  • Provides a practical guide to the use of SystemVerilog for both design and verification, unlike any other book currently available
  • Uses the Universal Verification Methodology (UVM) to build test-benches, in a manner accessible to novices
  • Covers the practical essentials needed for design, verification, synthesis and static timing analysis, which readers might otherwise have to find in several books
This book is an “A-Z” guide to using SystemVerilog for ASIC design, from conception to RTL coding, to synthesis and verification.  Readers will benefit from a thorough introduction to the powerful constructs and features of SystemVerilog. In addition, the verification methodology of Universal Verification Methodology (UVM) is used to build test-benches that allow for verification of complicated designs and synthesis basics are discussed, using the Synopsys Design Compiler (DC).  To complete this book’s package as a practical guide, readers are introduced to the fundamentals of static timing analysis.

Content Level » Professional/practitioner

Keywords » ASIC Design - ASIC Verification - SystemVerilog - SystemVerilog for Design - SystemVerilog for Verification - UVM - Universal Verification Methodology - VLSI Verification

Related subjects » Circuits & Systems - Communication Networks

Table of contents 

The SystemVerilog language.- Designing with SystemVerilog.- Verification with SytemVerilog.- Building environment and the DUT.- Synthesis.- Timing analysis.

Distribution rights 

Distribution rights for India: Delhi Book Store, New Delhi, India

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