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Engineering - Circuits & Systems | System-Level Validation - High-Level Modeling and Directed Test Generation Techniques

System-Level Validation

High-Level Modeling and Directed Test Generation Techniques

Chen, M., Qin, X., Koo, H.-M., Mishra, P.

2013, XXII, 250 p.

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  • Provides a comprehensive introduction to system-level validation
  • Describes high-level modeling using SystemC, UML and transaction-level models
  • Includes coverage of high-level modeling and directed test generation techniques as well efficient validation methodology using directed tests and assertions
  • Shows how to assure consistency between models with test/assertion refinement and reuse techniques across different levels of abstraction
This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures.  Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, including high-level modeling of designs and faults, automated generation of directed tests, and efficient validation methodology using directed tests and assertions.  The methodologies described in this book will help designers to improve the quality of their validation, performing as much validation as possible in the early stages of the design, while reducing the overall validation effort and cost.

Content Level » Professional/practitioner

Keywords » Automatic test generation - Embedded Systems - High-level modeling - Integrated Circuit Design - System-level verification - System-on-Chip verification - SystemC - Transaction level modeling - UML

Related subjects » Circuits & Systems - Communication Networks - Electronics & Electrical Engineering

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