Authors:
Integrates power estimation and reduction for high level synthesis, with low-power, high-level design
Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives
Covers techniques from RTL/gate-level to hardware software co-design
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Table of contents (13 chapters)
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Front Matter
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Back Matter
About this book
Authors and Affiliations
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, ECE Department, Virginia Polytechnic Institute and State, Blacksburg, USA
Sumit Ahuja
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, ECE Department, Virginia Tech, Blacksburg, USA
Avinash Lakshminarayana
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Bradley Dept. Electrical &, Computer Engineering, Virginia Tech, Blacksburg, USA
Sandeep Kumar Shukla
Bibliographic Information
Book Title: Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Authors: Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
DOI: https://doi.org/10.1007/978-1-4614-0872-7
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media, LLC 2012
Hardcover ISBN: 978-1-4614-0871-0Published: 21 October 2011
Softcover ISBN: 978-1-4899-8780-8Published: 23 October 2014
eBook ISBN: 978-1-4614-0872-7Published: 22 October 2011
Edition Number: 1
Number of Pages: XXII, 170
Topics: Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design