Sheibanyrad, Abbas, Pétrot, Frédéric, Jantsch, Axel (Eds.)
2011, X, 278 p.
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Provides a detailed overview of the state of error control methods for on-chip interconnects, including Error Control Coding, Double Sampling, and On-Line Testing Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links Presents techniques for managing intermittent and permanent errors using a non-interrupting in-line test method with spare wire replacement
Back Cover Copy
Integrated Circuits and Systems
3D-Integration for NoC-based SoC Architectures
This book investigates on the promises, challenges, and solutions for the 3D Integration (vertically stacking) of embedded systems connected via a network on a chip. It covers the entire architectural design approach for 3D-SoCs. 3D-Integration technologies, 3D-Design techniques, and 3D-Architectures have emerged as topics critical for current R&D leading to a broad range of products. This book presents a comprehensive, system-level overview of three-dimensional architectures and micro-architectures.
•Presents a comprehensive, system-level overview of three-dimensional architectures and micro-architectures;
•Covers the entire architectural design approach for 3D-SoCs;
•Includes state-of-the-art treatment of 3D-Integration technologies, 3D-Design techniques, and 3D-Architectures.
Content Level »Professional/practitioner
Keywords »Embedded Systems - Error Control in Network on Chip - Integrated Circuit Design - Network on Chip - On-chip interconnect