Authors:
- Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate
- Simulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patterns
- Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods
- Includes supplementary material: sn.pub/extras
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Table of contents (11 chapters)
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Front Matter
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Back Matter
About this book
Authors and Affiliations
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Dept. Electrical & Computer, Engineering, Worcester Polytechnic Institute, Worcester, USA
Zainalabedin Navabi
About the author
Bibliographic Information
Book Title: Digital System Test and Testable Design
Book Subtitle: Using HDL Models and Architectures
Authors: Zainalabedin Navabi
DOI: https://doi.org/10.1007/978-1-4419-7548-5
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media, LLC 2011
Hardcover ISBN: 978-1-4419-7547-8Published: 20 December 2010
Softcover ISBN: 978-1-4899-7927-8Published: 23 August 2016
eBook ISBN: 978-1-4419-7548-5Published: 10 December 2010
Edition Number: 1
Number of Pages: XVII, 435
Topics: Circuits and Systems, Mathematics, general, Philosophy, general