Power-Aware Testing and Test Strategies for Low Power Devices

Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices.

• Electronic Testing
• Low Power Design
• Low Power Testing
• Nanoscale Testing
• Nicolici
• Power Aware Testing
• Semiconductor Testing
• VLSI
• Wen
• power management
• semiconductor
• testing

• de Robotique de Microélectronique de, LIRMM - Laboratoire d'Informatique, Montpellier, France

  Patrick Girard

• Dept. Electrical &, McMaster University, Hamilton, Canada

  Nicola Nicolici

• Dept. Computer Science & Electronics, Kyushu Institute of Technology, Iizuka, Japan

  Xiaoqing Wen

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