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Engineering - Circuits & Systems | Language-driven Exploration and Implementation of Partially Re-configurable ASIPs

Language-driven Exploration and Implementation of Partially Re-configurable ASIPs

Chattopadhyay, A., Leupers, R., Meyr, H., Ascheid, G.

2009, IX, 203 p.

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  • This book presents a strong background and various perspectives of partially re-configurable processor design
  • The book goes through the history of partially re-configurable processor evolution, making the reader knowledgeable about the past research as well as the roadblocks faced over time
  • The partially re-configurable processor design requires an understanding of the key design problems in processor design as well as in re-configurable system design, both of which are active research topics at this moment; this book deals with these problems extensively
  • The complexity of re-configurable processor design thwarts the designers. A well-organized methodology, as presented in this book, highlighting the principles will help them tremendously
  • The book offers a modeling formalism as well as implementation methods, which can be used for stand-alone re-configurable system design

Increasing complexity of modern embedded systems demands system designers to ramp up their design productivity without compromising performance goals. This is promoted by modern Electronic System Level (ESL) techniques. Language-driven Exploration and Implementation of Partially Re-configurable ASIPs addresses an important segment of the ESL area by modeling partially re-configurable processors via high-level Architecture Description Language (ADL). This approach also hints an imminent evolution in the area of re-configurable system design.

Content Level » Professional/practitioner

Keywords » C-base - Design Space Exploration - Electronic System Level Design - Embedded System - Re-configurable Processor - Routing - Segment

Related subjects » Circuits & Systems - Communication Networks

Table of contents 

1 Introduction. 2 Background. 2.1 Processor Design: A Retrospection. 2.2 High-level Processor Modelling. 2.3 Library-based Processor Design. 2.4 Partially Re-configurable Processors: A Design Alternative. 2.5 Synopsis. 3 Related Work. 3.1 A Chronological Overview of the Expanding rASIP Design Space. 3.2 rASIP Design: High-level Modelling Approach. 3.3 rASIP Design: Library-based Approach. 3.4 Independent rASIP Design Tools. 3.5 Motivation. 3.6 Synopsis. 4 rASIP Design Space. 4.1 Architecture Design Points. 4.2 Language-based rASIP Modelling. 4.3 Language-based rASIP Design Flow. 4.4 Synopsis. 5 Pre-fabrication Design Space Exploration. 5.1 Pre-fabrication Design Decisions. 5.2 Application Characterization. 5.3 Software Tool-suite Generation for rASIP. 5.4 Partitioning the ISA: Coding Leakage Exploration. 5.5 Synopsis. 6 Pre-fabrication Design Implementation. 6.1 Base Processor Implementation. 6.2 Partitioning the Structure: Specification Aspects. 6.3 Partitioning the Structure: Implementation Aspects. 6.4 Latency: Multiple Clock Domain Implementation. 6.5 Automatic Interface Generation and Storage. 6.6 Background for FPGA Implementation. 6.7 FPGA Implementation: RTL Synthesis. 6.8 Background for Synthesis on FPGA. 6.9 FPGA Synthesis: Mapping and Clustering. 6.10 FPGA Synthesis: Placement and Routing. 6.11 Synopsis. 7 Post-fabrication Design Space Exploration and Implementation. 7.1 Post-fabrication Design Space Exploration. 7.2 Post-fabrication Design Implementation. 7.3 Synopsis. 8 Case Study. 8.1 Introduction. 8.2 Experiments with RISC-based Architecture. 8.3 Experiments with VLIW-based Architecture. 8.4 Experiments with Coarse-grained FPGA Exploration. 8.5 rASIP Modelling for W-CDMA. 9 Past, Present and Future. 9.1 Past. 9.2 Present. 9.3 Future.

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