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Extensive presentation of the leading research activities in HLS
Presentation of strengths of the available HLS technologies
User needs and application domains analysis
Overview of available EDA tool solutions and their applicability to design problems
The successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction. In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow - a VHDL/Verilog RTL specification, followed by logical and physical synthesis - is indeed no more suitable. Thus, actual complex SoCs need new ESL level tools in order to raise the specification abstraction level up to the algorithmic / behavioral one. However, in order to provide the designers with an efficient automated path to implementation, new high-level synthesis tools and approaches are required.
The main expectations from the system design teams concern both methods and tools supporting better management of the design complexity and reduction of the design cycle all together, breaking the trend to compromise evaluation of various design implementation options. Designing at higher levels of abstraction is an obvious way as it allows a better coping with the system design complexity, to verify earlier in the design process and to increase code reuse.
This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. High-Level Synthesis: from Algorithm to Digital Circuit should be on each designer’s and CAD developer’s shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design.
Preface: Giovanni di Michelli Chapter 1: User Needs. P. Urard, J. Yi, A.Gouraud Chapter 2: HLS: A Retrospective. Rajesh Gupta, Forrest Brewer Chapter 3: Catapult(R) Synthesis. Thomas Bollaert Chapter 4: Algorithmic Synthesis using PICO. S. Aditya, V. Kathail Chapter 5: High-Level SystemC Synthesis with Forte's Cynthesizer. Mike Meredith Chapter 6: AutoPilotTM: A Platform-Based ESL Synthesis System. Jason Cong, et al. Chapter 7: 'All-in-C' SoC Synthesis and Verification with CyberWorkBench. Kazutoshi Wakabayashi, Benjamin Schafer Chapter 8: Bluespec: A General-Purpose Approach to High Level Synthesis based on Atomic Transactions. Rishiyur Nikhil Chapter 9: GAUT: A High-Level Synthesis Tool for DSP Applications. Philippe Coussy, et al. Chapter 10: User Guided High Level Synthesis. Ivan Auge Chapter 11: Synthesis of DSP Algorithms from Infinite Precision Specifications. Christos-Savvas Bouganis, George Constantinides Chapter 12: High-Level Synthesis of loops using the Polyhedral Model. Steven Derien, et al. Chapter 13: Operation Scheduling: Algorithms and Applications. Gang Wang, Wenrui Gong, Ryan Kastner Chapter 14: Exploiting Bit-Level Design Techniques in Behavioural Synthesis. Maria Molina, Rafael Ruiz-Sautua, Jose M. Mendias, Roman Hermida Chapter 15: High-Level Synthesis Algorithms for Power and Temperature Minimization. Li Shang, Robert P. Dick, Niraj K. Jha