Digital VLSI Design with Verilog

1. Front Matter

   Pages I-XXIII

   PDF

2. Week 1 Class 1

   • John Williams

   Pages 1-20

3. Week 1 Class 2

   • John Williams

   Pages 21-42

4. Week 2 Class 1

   • John Williams

   Pages 43-60

5. Week 2 Class 2

   • John Williams

   Pages 61-82

6. Week 3 Class 1

   • John Williams

   Pages 83-99

7. Week 3 Class 2

   • John Williams

   Pages 101-112

8. Week 4 Class 1

   • John Williams

   Pages 113-144

9. Week 4 Class 2

   • John Williams

   Pages 145-168

10. Week 5 Class 1

    • John Williams

    Pages 169-184

11. Week 5 Class 2

    • John Williams

    Pages 185-194

12. Week 6 Class 1

    • John Williams

    Pages 195-210

13. Week 6 Class 2

    • John Williams

    Pages 211-230

14. Week 7 Class 1

    • John Williams

    Pages 231-242

15. Week 7 Class 2

    • John Williams

    Pages 243-258

16. Week 8 Class 1

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    Pages 259-277

17. Week 8 Class 2

    • John Williams

    Pages 279-293

18. Week 9 Class 1

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    Pages 295-310

19. Week 9 Class 2

    • John Williams

    Pages 311-335

20. Week 10 Class 1

    • John Williams

    Pages 337-360

Verilog and its usage has come a long way since its original invention in the mid-80s by Phil Moorby. At the time the average design size was around ten thousand gates, and simulation to validate the design was its primary usage. But between then and now designs have increased dramatically in size, and automatic logic synthesis from RTL has become the standard design ?ow for most design. Indeed, the language has evolved and been re-standardized too. Overtheyears,manybookshavebeenwrittenaboutVerilog.Myown,coauthored with Phil Moorby, had the goal of de?ning the language and its usage, providing - amples along the way. It has been updated with ?ve new editions as the language and its usage evolved. However this new book takes a very different and unique view; that of the designer. John Michael Williams has a long history of working and teaching in the ?eld of IC and ASIC design. He brings an indepth presentation of Verilog and how to use it with logic synthesis tools; no other Verilog book has dealt with this topic as deeply as he has. If you need to learn Verilog and get up to speed quickly to use it for synthesis, this book is for you. It is sectioned around a set of lessons including presentation and explanation of new concepts and approaches to design, along with lab sessions.

• HDL
• Scheduling
• VLSI
• simulation
• synthesis
• verification
• verilog

• SVTI Inc. Silicon Valley Technical Institute, San Jose CA 95110, USA

  John Williams

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