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Engineering - Circuits & Systems | Error Correction Codes for Non-Volatile Memories

Error Correction Codes for Non-Volatile Memories

Micheloni, Rino, Marelli, A., Ravasio, R.

2008, XII, 338 p.

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  • Provides a summary of the basics in coding theory found in typical coding books which are mainly focused on mathematical aspects
  • Includes examples of real applications of Hamming, BCH and Reed-Solomon codes
  • Describes ECC inside NOR and NAND Flash memories
  • Offers a collection of software routines for encoding and decoding in Flash memories

After "A Mathematical theory of communication" by C. E. Shannon, the 'Coding Theory' has begun its tremendous development as interface between Engineering, Computer Science and Mathematics. Contributions by mathematicians have focused on the design of new codes and the study of their properties, while contributions by engineers have focused on efficient implementations of encoding/decoding schemes. The research activities in Coding Theory have produced a vast range of different codes (with usually several alternative encoding/decoding algorithms), and their availability has pushed for new applications. Nowadays it is hard to find an electronic device which does not use codes: for example, we listen to music via heavily encoded audio CD's and we watch movies via encoded DVD's. There is at least one area where the use of encoding/decoding is not so developed, yet: Flash non-volatile memories. Flash memory high-density, low power, cost effectiveness, and scalable design make it an ideal choice to fuel the explosion of multimedia products, like USB keys, MP3 players, digital cameras and solid-state disk.

In ECC for Non-Volatile Memories the authors expose the basics of coding theory needed to understand the application to memories, as well as the relevant design topics, with reference to both NOR and NAND Flash architectures. A collection of software routines is also included for better understanding.

The authors form a research group (now at Qimonda) which is the typical example of a fruitful collaboration between mathematicians and engineers.

Content Level » Research

Keywords » BCH code - Code - ECC - Error-correcting Code - Flash memories - Galois field - Hamming code - Reed-Solomon code - algorithms - coding theory - non-volatile memories

Related subjects » Circuits & Systems - Electronics & Electrical Engineering - Materials - Optics & Lasers - Theoretical Computer Science

Table of contents 

Preface. Acknowledgements. 1. Basic coding theory. 1.1 Introduction. 1.2 Error detection and correction codes. 1.3 Probability of errors in a transmission channel. 1.4 ECC effect on error probability. 1.5 Basic definitions. Bibliography. 2 Error Correction Codes. 2.1 Hamming codes. 2.2 Reed-Muller codes. 2.3 Cyclic codes. Bibliography. 3 NOR Flash memories. 3.1 Introduction. 3.2 Read. 3.3 Program. 3.4 Erase. Bibliography. 4 NAND Flash memories. 4.1 Introduction. 4.2 Read. 4.3 Program. 4.4 Erase. Bibliography. 5 Reliability of Floating Gate Memories; A.Chimenton, M.Atti, P.Olivo. 5.1 Introduction. 5.2 Reliability issues in floating gate memories. 5.3 Conclusions. Bibliography. 6 Hardware implementation of Galois field operators. 6.1 Gray map. 6.2 Adders. 6.3 Constant multipliers. 6.4 Full multipliers. 6.5 Divider. 6.6 Linear Shift Register. Bibliography. 7 Hamming code for Flash memories. 7.1 Introduction. 7.2 NOR Single Bit. 7.3 NOR Flash multilevel memory. 7.4 Algorithmic Hamming code for big size blocks. Bibliography. 8 Cyclic codes for non volatile storage. 8.1 General structure. 8.2 Encoding. 8.3 Syndromes calculation. 8.4 Finding error locator polynomial. 8.5 Searching polynomial roots. 8.6 Computing error magnitude. 8.7 Decoding failures. 8.8 BCH vs Reed-Solomon. Bibliography. 9 BCH hardware implementation in NAND Flash memories. 9.1 Introduction. 9.2 Scaling of a ECC for MLC memories. 9.3 The system. 9.4 Parity computation. 9.5 Syndrome computation. 9.6 Berlekamp machine. 9.7 The Chien Machine. 9.8 Double Chien machine. 9.9 BCH embedded into the NAND memory. Bibliography. 10 Erasure technique. 10.1 Error disclosing capability for binary BCH codes. 10.2 Erasure concept in memories. 10.3 Binary erasure decoding. 10.4 Erasure and majority decoding. 10.5 Erasure decoding performances. Bibliography. Appendix A: Hamming code. A.1 Routine to find a parity matrix for a single bit or a single cell correction. A.2 Routine to find a parity matrix for a two errors correction code. A.3 Routine to find a parity matrix to correct 2 erroneous cells. Appendix B: BCH code. B.1 Routine to generate the BCH code parameters. B.2 Routine to encode a message. B.3 Routine to calculate the syndromes of a read message. B.4 Routine to calculate the evaluation matrices. B.5 Routines to compute operations in a Galois field. B.6 Routine to calculate the lambda coefficients. B.7 Routine to execute Chien algorithm. B.8 Routine to find the matrix to execute the multiplication by alpha. Appendix C: the Galois field GF(24). Appendix D: the parallel BCH code. D.1 Routine to get the matrix for the encoding. D.2 Routine to get matrices for the syndromes. D.3 Routine to get the matrix for the multiplier. D.4 Routine to calculate the coefficients of the error locator polynomial. D.5 Routine to get matrices for the Chien machine. D.6 Global matrix optimization for the Chien machine. D.7 BCH flow overview. Appendix E: erasure decoding technique. E.1 Subroutines. E.2 Erasure decoding routine. Index.

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