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Engineering - Circuits & Systems | CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies - Process-Aware SRAM (Authors and Editors)

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

Process-Aware SRAM Design and Test

Pavlov, Andrei, Sachdev, Manoj

2008, XVI, 194 p.

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Prof. Sachdev has authored several successful books with Springer

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    CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

    Process-Aware SRAM Design and Test

    Series: Frontiers in Electronic Testing, Vol. 40

    Pavlov, Andrei, Sachdev, Manoj 2008

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    Defect Oriented Testing for CMOS Analog and Digital Circuits

    Series: Frontiers in Electronic Testing, Vol. 10

    Sachdev, Manoj 1999, or go to the Latest Edition

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    ISBN 978-1-4757-4926-7
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  • Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
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    Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

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    ESD Protection Device and Circuit Design for Advanced CMOS Technologies

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