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  • © 2004

Testing Static Random Access Memories

Defects, Fault Models and Test Patterns

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Part of the book series: Frontiers in Electronic Testing (FRET, volume 26)

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Softcover Book USD 109.99
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Table of contents (11 chapters)

  1. Front Matter

    Pages i-xx
  2. Introductory

    1. Front Matter

      Pages 1-1
    2. Introduction

      • Said Hamdioui
      Pages 3-15
    3. Semiconductor memory architecture

      • Said Hamdioui
      Pages 17-35
    4. Space of memory faults

      • Said Hamdioui
      Pages 37-64
    5. Preparation for circuit simulation

      • Said Hamdioui
      Pages 65-84
  3. Testing single-port and two-port SRAMs

    1. Front Matter

      Pages 85-85
    2. Experimental analysis of two-port SRAMs

      • Said Hamdioui
      Pages 87-103
    3. Tests for single-port and two-port SRAMs

      • Said Hamdioui
      Pages 105-134
    4. Testing restricted two-port SRAMs

      • Said Hamdioui
      Pages 135-145
  4. Testing p-port SRAMs

    1. Front Matter

      Pages 147-147
    2. Experimental analysis of p-port SRAMs

      • Said Hamdioui
      Pages 149-160
    3. Tests for p-port SRAMs

      • Said Hamdioui
      Pages 161-174
    4. Testing restricted p-port SRAMs

      • Said Hamdioui
      Pages 175-184
    5. Trends in embedded memory testing

      • Said Hamdioui
      Pages 185-196
  5. Back Matter

    Pages 197-221

About this book

Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed.
Features:
-Fault primitive based analysis of memory faults,
-A complete framework of and classification memory faults,
-A systematic way to develop optimal and high quality memory test algorithms,
-A systematic way to develop test patterns for any multi-port SRAM,
-Challenges and trends in embedded memory testing.

Reviews

From the reviews:

"Static random access memories (SRAMs) enjoy a strategic position in the microelectronic industry. … This book concentrates on the study of fault modeling, testing and test strategies for SRAMs. … The book provides a well-written coverage in the area of single-, two- and n-port SRAM testing, fault modeling, and simulation. It is well-organized and very timely. … The book promises to make valuable contribution to the education of graduate students … . I highly recommend this book … ." (Mile Stojcev, Microelectronics Reliability, Vol. 45, 2005)

Authors and Affiliations

  • Delft University of Technology, The Netherlands

    Said Hamdioui

Bibliographic Information

Buy it now

Buying options

Softcover Book USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access