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Discusses all aspects of the topic and contains industrial and academic contributions
Includes modeling software
Fine- and Coarse-Grain Reconfigurable Computing gives the basic concepts and building blocks for the design of Fine- (or FPGA) and Coarse-Grain Reconfigurable Architectures. Recently-developed integrated architecture design and software-supported design flow of FPGA and coarse-grain reconfigurable architecture are also described. Part I consists of two extensive surveys of FPGA and Coarse-Grain Reconfigurable Architectures: The FPGA technology is defined, which includes architecture, logic block structure, interconnect, and configuration methods and existing fine-grain reconfigurable architectures emerged from both academia and industry. Additionally, the implementation techniques and CAD tools developed to facilitate the implementation of a system in reconfigurable hardware by the industry and academia are provided. In addition the features, the advantages and limitations of the coarse-grain reconfigurable systems, the specific issues that should be addressed during the design phase, as well as representative existing coarse-grain reconfigurable systems are explained. In Part II, case studies, innovative research results about reconfigurable architectures and design frameworks from three projects AMDREL, MOLEN and ADRES&DRESC, and, a new classification according to microcoded architectural criteria are described. Fine- and Coarse-Grain Reconfigurable Computing is an essential reference for researchers and professionals and can be used as a textbook by undergraduate, graduate students and professors. Foreword by Yale Patt, Jim Smith and Mateo Valero
Chapter 1: A Survey of Fine-Grain Reconfigurable Architectures and CAD tools; K. Tatas, K. Siozios and D. Soudris
Chapter 2: A Survey of Coarse-Grain Reconfigurable Architectures and CAD tools; G. Theodoridis, Stamatis Vassiliadis and D. Soudris
Part II: Case Studies
Chapter 3: AMDREL: A Novel Low-Energy FPGA Architecture and Supporting CAD Tool Design Flow; D. Soudris, K. Tatas, K. Siozios, G. Koutroumpezis, S. Nikolaidis, S. Siskos, N. Vassiliadis, V. Kalenteridis, H. Pournara and I. Pappas
Chapter 4: A coarse-grain dynamically reconfigurable system and compilation framework; Marcos Sanchez-Elez, Milagros Fernandez, Nader Bagherzadeh, Roman Hermida, Fadi Kurdahi and Rafael Maestre
Chapter 5: Polymorphic Instruction Set Computers; Georgi Kuzmanov and Stamatis Vassiliadis
Chapter 6: ADRES&DRESC: Architecture And Compiler For Coarse-Grain Reconfigurable Processors; B. Mei, M. Berekovic, J-Y. Mignolet
Chapter 7: A Taxonomy of Field-Programmable Custom Computing Machines: An architectural approach; Mihai SIMA, Stamatis Vassiliadis and Sorin Cotofana