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Engineering - Circuits & Systems | Design for Manufacturability and Yield for Nano-Scale CMOS

Design for Manufacturability and Yield for Nano-Scale CMOS

Chiang, Charles, Kawa, Jamil

2007, XXVII, 255 p.

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  • Addressing a new topic (DFM/DFY) critical at 90 nm and beyond
  • No book available today with comprehensive coverage of this topic
  • Book covers all CAD/CAE aspects of a SOC design flow

As we approach the 32 nm CMOS technology node the design and manufacturing communities are dealing with a lithography system that has to print circuit artifacts that are significantly less than half the wavelength of the light source used, with new materials, with tighter pitches, and higher aspect ratio metallurgies. This reality has resulted in three main manufacturability issues that have to be addressed: printability, planarization, and intra-die variability. Addressing in depth the fundamentals impacting those three issues at all the stages of the design process is not a luxury one can ignore. Manufacturability and yield are now one and the same and are no longer a fabrication, packaging, and test concerns; they are the concern of the whole IC community. Yield and manufacturability have to be designed in, and they are everybody’s responsibility.

Design for Manufacturability and Yield for Nano-Scale CMOS walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells and how to yield-grade libraries for critical area and lithography artifacts through place and route, CMP model based simulation and dummy-fill insertion, mask planning, simulation and manufacturing, and through statistical design and statistical timing closure of the design. It alerts the designer to the pitfalls to watch for and to the good practices that can enhance a design’s manufacturability and yield. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development.

Content Level » Research

Keywords » CAD (Computer aided design) - CAE (Computer aided engineering) - CMOS - Standard - classification - computer-aided design (CAD) - computer-aided engineering (CAE) - design - development - integrated circuit - layout - model - nano-scale - simulation - tables

Related subjects » Circuits & Systems - Communication Networks - Electronics & Electrical Engineering - Information Systems and Applications - Nanotechnology - Software Engineering

Table of contents 

1. Introduction of DFM/DFY. a. What is DFM/DFY ? historical perspective. b. Why is it becoming ever so critical? c. DFM categories & classifications. d. How do various DFM solutions tie up with specific design flows. e. DFM & DFY are intertwined. 2. Random Defects. a. CAA. b. Improving CAA. c. Cell library yield grading based on CAA. 3. Systematic yield. a. Lithography. 4. Systematic yield. b. CMP 5. Parametric yield. a. Intro. b. Timing aspects. c. Power considerations. 6. Design for yield. a. analysis. b. prediction. c. enhancement. 7. Summary and Conclusions

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