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Simultaneous Switching Noise of CMOS Devices and Systems

  • Book
  • © 1994

Overview

Authors:
  1. Ramesh Senthinathan

    1. Advanced Packaging Development Center (APDC), Motorola, Inc., USA

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  2. John L. Prince

    1. Center for Electronic Packaging Research (CEPR), The University of Arizona, USA

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    You can also search for this author in PubMed   Google Scholar

Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 249)

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Table of contents (11 chapters)

  1. Front Matter

    Pages i-xxi
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  2. Introduction

    • Ramesh Senthinathan, John L. Prince
    Pages 1-7

  3. Packaged/Scaled Cmos Devices

    • Ramesh Senthinathan, John L. Prince
    Pages 9-18

  4. Methods of Calculating Simultaneous Switching Noise

    • Ramesh Senthinathan, John L. Prince
    Pages 19-32

  5. Power Distribution Inductance Modeling

    • Ramesh Senthinathan, John L Prince
    Pages 33-51

  6. Signal Conductors Over a Perforated Reference Plane

    • Ramesh Senthinathan, John L. Prince
    Pages 53-84

  7. Dynamic Noise Immunity, and Skewing/Damping SSN Waveform

    • Ramesh Senthinathan, John L. Prince
    Pages 85-97

  8. Application Specific Output Drivers to Reduce SSN

    • Ramesh Senthinathan, John L. Prince
    Pages 99-115

  9. SSN Simulator Architecture

    • Ramesh Senthinathan, John L. Prince
    Pages 117-128

  10. Signal Conductors Over a Noisy Reference Plane

    • Ramesh Senthinathan, John L. Prince
    Pages 129-156

  11. Conclusions

    • Ramesh Senthinathan, John L. Prince
    Pages 157-159

  12. Discussion and Future Work

    • Ramesh Senthinathan, John L. Prince
    Pages 161-165

  13. Back Matter

    Pages 167-205
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Keywords

About this book

This monograph presents our recent research on Simultaneous Switching Noise (SSN) and related issues for CMOS based systems. Although some SSN related work was previously reported in the literature, it were mainly for Emitter Coupled Logic (ECL) gates using Bipolar Junction Transistors (BJTs). This present work covers in-depth analysis on estimating SSN and its impact for CMOS based devices and systems. At present semiconductor industries are moving towards scaled CMOS devices and reduced supply voltage. SSN together with coupled noise may limit the packing density, and thereby the frequency of operation of packaged systems. Our goal is to provide efficient and yet reliable methodologies and algorithms to estimate the overall noise containment in single chip and multi-chip package assemblies. We hope that the techniques and results described in this book will be useful as guides for design, package, and system engineers and academia working in this area. Through this monograph, we hope that we have shown the necessity of interactions that are essential between chip design, system design and package design engineers to design and manufacture optimal packaged systems. Work reported in this monograph was partially supported by the grant from Semiconductor Research Corporation (SRC Contract No. 92-MP-086).

Authors and Affiliations

  • Advanced Packaging Development Center (APDC), Motorola, Inc., USA

    Ramesh Senthinathan

  • Center for Electronic Packaging Research (CEPR), The University of Arizona, USA

    John L. Prince

Bibliographic Information

  • Book Title: Simultaneous Switching Noise of CMOS Devices and Systems

  • Authors: Ramesh Senthinathan, John L. Prince

  • Series Title: The Springer International Series in Engineering and Computer Science

  • DOI: https://doi.org/10.1007/978-1-4615-3204-0

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Springer Science+Business Media New York 1994

  • Hardcover ISBN: 978-0-7923-9400-6Published: 30 November 1993

  • Softcover ISBN: 978-1-4613-6406-1Published: 23 February 2014

  • eBook ISBN: 978-1-4615-3204-0Published: 27 November 2013

  • Series ISSN: 0893-3405

  • Edition Number: 1

  • Number of Pages: XXI, 205

  • Topics: Circuits and Systems, Electrical Engineering

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