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Table of contents (13 chapters)
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Front Matter
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Back Matter
About this book
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.
Bibliographic Information
Book Title: Advanced ASIC Chip Synthesis
Book Subtitle: Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime®
Authors: Himanshu Bhatnagar
DOI: https://doi.org/10.1007/b117024
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Science+Business Media, LLC, part of Springer Nature 2002
Hardcover ISBN: 978-0-7923-7644-6Published: 31 December 2001
Softcover ISBN: 978-1-4757-7629-4Published: 23 May 2013
eBook ISBN: 978-0-306-47507-8Published: 08 May 2007
Edition Number: 2
Number of Pages: XXVI, 328
Topics: Circuits and Systems, Electrical Engineering, Computer-Aided Engineering (CAD, CAE) and Design