Authors:
- Provides state-of-the-art research on the challenges to test, diagnose and tolerate faults in NoC-based systems
- Includes numerous, current test strategies, including re-use of the network for core testing, test scheduling for the NoC reuse, test access methods and interface, efficient re-use of the network, and power-aware and thermal-aware NoC-based SoC testing
- Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings
- Includes supplementary material: sn.pub/extras
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Table of contents (10 chapters)
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Front Matter
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Back Matter
About this book
This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of Network on Chip-based systems. It is the first book dedicated to the quality aspects of NoC-based systems and will serve as an invaluable reference to the problems, challenges, solutions, and trade-offs related to designing and implementing state-of-the-art, on-chip communication architectures.
Authors and Affiliations
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Instituto de Informática, Porto Alegre, Brazil
Érika Cota
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PUCRS, Faculdade de Informática, Hardware Design Support Group (GAPH), Porto Alegre, Brazil
Alexandre Morais Amory
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CEITEC SA, Porto Alegre, Brazil
Marcelo Soares Lubaszewski
Bibliographic Information
Book Title: Reliability, Availability and Serviceability of Networks-on-Chip
Authors: Érika Cota, Alexandre Morais Amory, Marcelo Soares Lubaszewski
DOI: https://doi.org/10.1007/978-1-4614-0791-1
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media, LLC 2012
Hardcover ISBN: 978-1-4614-0790-4Published: 22 September 2011
Softcover ISBN: 978-1-4899-7350-4Published: 25 November 2014
eBook ISBN: 978-1-4614-0791-1Published: 23 September 2011
Edition Number: 1
Number of Pages: XIII, 209
Topics: Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design