Skip to main content
SpringerLink
Log in

Hierarchical Annotated Action Diagrams

An Interface-Oriented Specification and Verification Method

  • Book
  • © 1998

Overview

Authors:
  1. E. Cerny

    1. Université de Montréal, Canada

    View author publications

    You can also search for this author in PubMed   Google Scholar

  2. B. Berkane

    1. Nortel Semiconductors, USA

    View author publications

    You can also search for this author in PubMed   Google Scholar

  3. P. Girodias

    1. Université de Montréal, Canada

    View author publications

    You can also search for this author in PubMed   Google Scholar

  4. K. Khordoc

    1. McGill University, Canada

    View author publications

    You can also search for this author in PubMed   Google Scholar

This is a preview of subscription content, log in via an institution to check access.

Access this book

Log in via an institution
eBook USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (8 chapters)

  1. Front Matter

    Pages i-xvi
    Download chapter PDF

  2. Introduction

    • E. Cerny, B. Berkane, P. Girodias, K. Khordoc
    Pages 1-8

  3. Overview of HAAD Method

    • E. Cerny, B. Berkane, P. Girodias, K. Khordoc
    Pages 9-22

  4. Formal Characterization of HAAD

    • E. Cerny, B. Berkane, P. Girodias, K. Khordoc
    Pages 23-48

  5. HAAD VHDL Model

    • E. Cerny, B. Berkane, P. Girodias, K. Khordoc
    Pages 49-68

  6. Consistency, Causality and Compatibility

    • E. Cerny, B. Berkane, P. Girodias, K. Khordoc
    Pages 69-97

  7. Interface Verification using CLP

    • E. Cerny, B. Berkane, P. Girodias, K. Khordoc
    Pages 99-132

  8. Example: Interfacing ARM7 and a Static RAM

    • E. Cerny, B. Berkane, P. Girodias, K. Khordoc
    Pages 133-165

  9. Summary and Recent Developments

    • E. Cerny, B. Berkane, P. Girodias, K. Khordoc
    Pages 167-171

  10. Back Matter

    Pages 173-211
    Download chapter PDF
Back to top

Keywords

About this book

Standardization of hardware description languages and the availability of synthesis tools has brought about a remarkable increase in the productivity of hardware designers. Yet design verification methods and tools lag behind and have difficulty in dealing with the increasing design complexity. This may get worse because more complex systems are now constructed by (re)using Intellectual Property blocks developed by third parties. To verify such designs, abstract models of the blocks and the system must be developed, with separate concerns, such as interface communication, functionality, and timing, that can be verified in an almost independent fashion. Standard Hardware Description Languages such as VHDL and Verilog are inspired by procedural `imperative' programming languages in which function and timing are inherently intertwined in the statements of the language. Furthermore, they are not conceived to state the intent of the design in a simple declarative way that contains provisions for design choices, for stating assumptions on the environment, and for indicating uncertainty in system timing.
Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method presents a description methodology that was inspired by Timing Diagrams and Process Algebras, the so-called Hierarchical Annotated Diagrams. It is suitable for specifying systems with complex interface behaviors that govern the global system behavior. A HADD specification can be converted into a behavioral real-time model in VHDL and used to verify the surrounding logic, such as interface transducers. Also, function can be conservatively abstracted away and the interactions between interconnected devices can be verified using Constraint Logic Programming based on Relational Interval Arithmetic.
Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method is ofinterest to readers who are involved in defining methods and tools for system-level design specification and verification. The techniques for interface compatibility verification can be used by practicing designers, without any more sophisticated tool than a calculator.

Authors and Affiliations

  • Université de Montréal, Canada

    E. Cerny, P. Girodias

  • Nortel Semiconductors, USA

    B. Berkane

  • McGill University, Canada

    K. Khordoc

Bibliographic Information

Publish with us

Policies and ethics

Back to top

Search

Navigation