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  • Book
  • © 2006

The Core Test Wrapper Handbook

Rationale and Application of IEEE Std. 1500™

  • Guides engineers through the process of building a 1500 wrapper
  • Provides insight into the rules and recommendations of IEEE Std. 1500 Focus on practical design considerations inherent to the application of IEEE Std. 1500 by discussing design choices and other decisions relevant to this IEEE standard
  • The authors provide background information about some of the choices and decisions made throughout the design of IEEE Std. 1500
  • Includes supplementary material: sn.pub/extras

Part of the book series: Frontiers in Electronic Testing (FRET, volume 35)

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Table of contents (12 chapters)

  1. Front Matter

    Pages i-xxix
  2. Introduction

    Pages 1-1
  3. Illustration Example

    Pages 21-28
  4. Instruction Types

    Pages 77-129
  5. Design of the WBR

    Pages 131-179
  6. Design of the WBY

    Pages 181-186
  7. Design of the WIR

    Pages 187-216
  8. Hierarchical Cores

    Pages 217-220
  9. Back Matter

    Pages 273-276

About this book

In the early to mid-1990's while working at what was then Motorola Se- conductor, business changes forced my multi-hundred dollar microprocessor to become a tens-of-dollars embedded core. I ran into first hand the problem of trying to deliver what used to be a whole chip with something on the order of over 400 interconnect signals to a design team that was going to stuff it into a package with less than 220 signal pins and surround it with other logic. I also ran into the problem of delivering microprocessor specification verifi- tion – a microprocessor is not just about the functions and instructions included with the instruction set, but also the MIPs rating at some given f- quency. I faced two dilemmas: one, I could not deliver functional vectors without significant development of off-core logic to deal with the reduced chip I/O map (and everybody's I/O map was going to be a little different); and two, the JTAG (1149. 1) boundary scan ring that was around my core when it was a chip was going to be woefully inadequate since it did not support - speed signal application and capture and independent use separate from my core. I considered the problem at length and came up with my own solution that was predominantly a separate non-JTAG scan test wrapper that supported at-speed application of launch-capture cycles using the system clock. But my problems weren't over at that point either.

Bibliographic Information

Buy it now

Buying options

eBook USD 89.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 119.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access