Overview
- Offers readers a systematic and comprehensive literature review of fast and compact machine learning algorithms on IoT devices
- Provides various techniques on neural network model optimization such as bit-width truncation and matrix (tensor) decomposition
- Focuses on machine learning architecture design on both CMOS technology and RRAM technology to provide energy-efficient hardware solutions
- Illustrates design and analysis for real-life applications such as indoor positioning, energy management and network security in smart buildings
Part of the book series: Computer Architecture and Design Methodologies (CADM)
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Table of contents (6 chapters)
Keywords
About this book
This book presents the latest techniques for machine learning based data analytics on IoT edge devices. A comprehensive literature review on neural network compression and machine learning accelerator is presented from both algorithm level optimization and hardware architecture optimization. Coverage focuses on shallow and deep neural network with real applications on smart buildings. The authors also discuss hardware architecture design with coverage focusing on both CMOS based computing systems and the new emerging Resistive Random-Access Memory (RRAM) based systems. Detailed case studies such as indoor positioning, energy management and intrusion detection are also presented for smart buildings.
Authors and Affiliations
Bibliographic Information
Book Title: Compact and Fast Machine Learning Accelerator for IoT Devices
Authors: Hantao Huang, Hao Yu
Series Title: Computer Architecture and Design Methodologies
DOI: https://doi.org/10.1007/978-981-13-3323-1
Publisher: Springer Singapore
eBook Packages: Intelligent Technologies and Robotics, Intelligent Technologies and Robotics (R0)
Copyright Information: Springer Nature Singapore Pte Ltd. 2019
Hardcover ISBN: 978-981-13-3322-4Published: 18 December 2018
eBook ISBN: 978-981-13-3323-1Published: 07 December 2018
Series ISSN: 2367-3478
Series E-ISSN: 2367-3486
Edition Number: 1
Number of Pages: IX, 149
Number of Illustrations: 15 b/w illustrations, 61 illustrations in colour
Topics: Computational Intelligence, Processor Architectures, Optimization