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This book constitutes the refereed proceedings of the 15th International Conference on Compiler Construction, CC 2006, held in Vienna, Austria, in March 2006 as part of ETAPS.
The 17 revised full papers presented together with three tool demonstration papers and one invited paper were carefully reviewed and selected from 71 submissions. The papers are organized in topical sections on program analysis, dynamic analysis, tool demonstrations, optimization, code generation, and register allocation.
Content Level »Research
Keywords »Fusion - Java - algorithms - code generation - compiler construction - compiler optimization - dynamic analysis - language processing - model checking - optimization - program analysis - program compilation - programming language design - real-time - visualization
Invited Talk.- Using Dependent Types to Port Type Systems to Low-Level Languages.- Program Analysis.- Interprocedural Dataflow Analysis in the Presence of Large Libraries.- Efficient Flow-Sensitive Interprocedural Data-Flow Analysis in the Presence of Pointers.- Path-Based Reuse Distance Analysis.- Context-Sensitive Points-to Analysis: Is It Worth It?.- Dynamic Analysis.- Selective Runtime Memory Disambiguation in a Dynamic Binary Translator.- Accurately Choosing Execution Runs for Software Fault Localization.- Tool Demonstrations.- Demonstration: On-Line Visualization and Analysis of Real-Time Systems with TuningFork.- Data-Flow Analysis as Model Checking Within the jABC.- The CGiS Compiler—A Tool Demonstration.- Optimization.- Loop Transformations in the Ahead-of-Time Optimization of Java Bytecode.- Hybrid Optimizations: Which Optimization Algorithm to Use?.- A Fresh Look at PRE as a Maximum Flow Problem.- Performance Characterization of the 64-bit x86 Architecture from Compiler Optimizations’ Perspective.- Code Generation.- Lightweight Lexical Closures for Legitimate Execution Stack Access.- Polyhedral Code Generation in the Real World.- Iterative Collective Loop Fusion.- Converting Intermediate Code to Assembly Code Using Declarative Machine Descriptions.- Register Allocation.- SARA: Combining Stack Allocation and Register Allocation.- Register Allocation for Programs in SSA-Form.- Enhanced Bitwidth-Aware Register Allocation.