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Transactions on High-Performance Embedded Architectures and Compilers II

  • Book
  • © 2009

Overview

Editors:
  1. Per Stenström

    1. Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 5470)

Part of the book sub series: Transactions on High-Performance Embedded Architectures and Compilers (THIPEAC)

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Table of contents (16 chapters)

  1. Front Matter

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  2. Special Section on High-Performance Embedded Architectures and Compilers

    1. Front Matter

      Pages 1-1
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    2. Introduction

      • Per Stenström, David Whalley
      Pages 3-3

    3. Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches

      • Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras
      Pages 4-22

    4. Compiler-Assisted Memory Encryption for Embedded Processors

      • Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy
      Pages 23-44

    5. Branch Predictor Warmup for Sampled Simulation through Branch History Matching

      • Simon Kluyskens, Lieven Eeckhout
      Pages 45-64

    6. Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems

      • Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson
      Pages 65-84

    7. Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization

      • Chunling Hu, Daniel A. Jiménez, Ulrich Kremer
      Pages 85-104

  3. Regular Papers

    1. Front Matter

      Pages 105-105
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    2. Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors

      • Woojin Choi, Seok-Jun Park, Michel Dubois
      Pages 107-127

    3. Fetch Gating Control through Speculative Instruction Window Weighting

      • Hans Vandierendonck, André Seznec
      Pages 128-148

    4. Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers

      • Minwook Ahn, Yunheung Paek
      Pages 149-172

    5. Linux Kernel Compaction through Cold Code Swapping

      • Dominique Chanet, Javier Cabezas, Enric Morancho, Nacho Navarro, Koen De Bosschere
      Pages 173-200

    6. Complexity Effective Bypass Networks

      • Aneesh Aggarwal
      Pages 201-221

    7. A Context-Parameterized Model for Static Analysis of Execution Times

      • Christine Rochange, Pascal Sainrat
      Pages 222-241

    8. Reexecution and Selective Reuse in Checkpoint Processors

      • Amit Golander, Shlomo Weiss
      Pages 242-268

    9. Compiler Support for Code Size Reduction Using a Queue-Based Processor

      • Arquimedes Canedo, Ben Abderazek, Masahiro Sowa
      Pages 269-285

    10. Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC

      • Khaled Z. Ibrahim, Smail Niar
      Pages 286-306

    11. Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories

      • Patrick Mahoney, Yvon Savaria, Guy Bois, Patrice Plante
      Pages 307-325

  4. Back Matter

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Keywords

About this book

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems.

This second issue contains 15 papers carefully reviewed and selected out of 31 submissions and is divided into two sections. The first section contains extended versions of the top five papers from the 2nd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2007) held in Ghent, Belgium, in January 2007.  The second section consists of ten papers covering topics such as microarchitecture, memory systems, code generation, and performance modeling.

Editors and Affiliations

  • Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden

    Per Stenström

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