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Cryptographic Hardware and Embedded Systems - CHES 2000

Second International Workshop Worcester, MA, USA, August 17-18, 2000 Proceedings

  • Conference proceedings
  • © 2000

Overview

Editors:
  1. Çetin K. Koç

    1. Oregon State University, Oregon, USA

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    You can also search for this editor in PubMed   Google Scholar

  2. Christof Paar

    1. ECE Dept., Cryptography and Information Security (CRIS) Group, WPI, Worcester, USA

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 1965)

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Table of contents (27 papers)

  1. Front Matter

    Pages I-XI
    Download chapter PDF

  2. Invited Talk

    1. Software Implementation of Elliptic Curve Cryptography over Binary Fields

      • Darrel Hankerson, Julio López Hernandez, Alfred Menezes
      Pages 1-24

  3. Implementation of Elliptic Curve Cryptosystems

    1. Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA

      • Souichi Okada, Naoya Torii, Kouichi Itoh, Masahiko Takenaka
      Pages 25-40

    2. A High-Performance Reconfigurable Elliptic Curve Processor for GF(2m)

      • Gerardo Orlando, Christof Paar
      Pages 41-56

    3. Fast Implementation of Elliptic Curve Defined over GF(pm) on CalmRISC with MAC2424 Coprocessor

      • Jae Wook Chung, Sang Gyoo Sim, Pil Joong Lee
      Pages 57-70

  5. Hardware Implementation of Block Ciphers

    1. A Comparative Study of Performance of AES Final Candidates Using FPGAs

      • Andreas Dandalis, Viktor K. Prasanna, Jose D.P. Rolim
      Pages 125-140

    2. A Dynamic FPGA Implementation of the Serpent Block Cipher

      • Cameron Patterson
      Pages 141-155

    3. A 12 Gbps DES Encryptor/Decryptor Core in an FPGA

      • Steve Trimberger, Raymond Pang, Amit Singh
      Pages 156-163

    4. A 155 Mbps Triple-DES Network Encryptor

      • Herbert Leitold, Wolfgang Mayerwieser, Udo Payer, Karl Christian Posch, Reinhard Posch, Johannes Wolkerstorfer
      Pages 164-174

  6. Hardware Architectures

    1. An Energy Efficient Reconfigurable Public-Key Cryptography Processor Architecture

      • James Goodman, Anantha Chandrakasan
      Pages 175-190

    2. High-Speed RSA Hardware Based on Barret’s Modular Reduction Method

      • Johann Großschädl
      Pages 191-203

    3. Data Integrity in Hardware for Modular Arithmetic

      • Colin D. Walter
      Pages 204-215

    4. A Design for Modular Exponentiation Coprocessor in Mobile Telecommunication Terminals

      • Takehiko Kato, Satoru Ito, Jun Anzai, Natsume Matsuzaki
      Pages 216-228

  7. Invited Talk

    1. How to Explain Side-Channel Leakage to Your Kids

      • David Naccache, Michael Tunstall
      Pages 229-230

  8. Power Analysis Attacks

    1. On Boolean and Arithmetic Masking against Differential Power Analysis

      • Jean-Sébastien Coron, Louis Goubin
      Pages 231-237

    2. Using Second-Order Power Analysis to Attack DPA Resistant Software

      • Thomas S. Messerges
      Pages 238-251
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Keywords

Editors and Affiliations

  • Oregon State University, Oregon, USA

    Çetin K. Koç

  • ECE Dept., Cryptography and Information Security (CRIS) Group, WPI, Worcester, USA

    Christof Paar

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