Skip to main content
SpringerLink
Log in

VLSI Design and Test

17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Proceedings

  • Conference proceedings
  • © 2013

Overview

Editors:
  1. Manoj Singh Gaur

    1. MNIT, Jaipur, India

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  2. Mark Zwolinski

    1. University of Southampton, UK

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  3. Vijay Laxmi

    1. MNIT, Jaipur, India

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  4. Dharmendra Boolchandani

    1. MNIT, Jaipur, India

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  5. Virendra Sing

    1. IIT Bombay, Mumbai, India

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  6. Adit D. Sing

    1. Auburn University, USA

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  • 17th International Symposium on VLSI Design and Test, VDAT 2013

Part of the book series: Communications in Computer and Information Science (CCIS, volume 382)

This is a preview of subscription content, log in via an institution to check access.

Access this book

Log in via an institution
eBook USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (44 papers)

  1. Front Matter

    Download chapter PDF

  2. Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM

    • Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma
    Pages 1-9

  3. A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator

    • Gudlavalleti Rajahari, Yashu Anand Varshney, Subash Chandra Bose
    Pages 10-18

  4. A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain Amplifier

    • Vivek Verma, Chetan D. Parikh
    Pages 19-25

  5. An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network

    • R. K. Naga Mahesh, Akash Ganesan, Manchi Pavan Kumar, Roy Paily
    Pages 26-34

  6. Computational Functions’ VLSI Implementation for Compressed Sensing

    • Shrirang Korde, Amol Khandare, Raghavendra Deshmukh, Rajendra Patrikar
    Pages 35-43

  7. A Novel Input Capacitance Modeling Methodology for Nano-Scale VLSI Standard Cell Library Characterization

    • Akhtar W. Alam, Esakkimuthu Dhakshinamoorthy, Prince Mathew, Narender Ponna
    Pages 44-48

  8. An Area Efficient Wide Range On-Chip Delay Measurement Architecture

    • Rahul Krishnamurthy, G. K. Sharma
    Pages 49-58

  9. 10 Gbps Current Mode Logic I/O Buffer

    • Akhil Rathore, Chetan D Parikh
    Pages 59-65

  10. Kapees: A New Tool for Standard Cell Placement

    • Sameer Pawanekar, Kalpesh Kapoor, Gaurav Trivedi
    Pages 66-73

  11. Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization

    • Kanchan Manna, Shailesh Singh, Santanu Chattopadhyay, Indranil Sengupta
    Pages 74-82

  12. Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence

    • Sumanta Pyne, Ajit Pal
    Pages 83-93

  13. Design and Simulation of Bulk Micromachined Accelerometer for Avionics Application

    • Amit Sharma, Ravindra Mukhiya, S. Santosh Kumar, B. D. Pant
    Pages 94-99

  14. Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology

    • Himadri Singh Raghav, Sachin Maheshwari, B. Prasad Singh
    Pages 100-107

  15. Characterization of Logical Effort for Improved Delay

    • Sachin Maheshwari, Himadri Singh Raghav, Anu Gupta
    Pages 108-117

  16. A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance

    • Ratul Kumar Baruah, Roy P. Paily
    Pages 118-127

  17. An Improved g m /I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design

    • Somnath Paul, Abhijit Dana, Soumya Pandit
    Pages 128-137

  18. An Efficient RF Energy Harvester with Tuned Matching Circuit

    • Sachin Agrawal, Sunil Pandey, Jawar Singh, P. N. Kondekar
    Pages 138-145

  19. A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits

    • Surabhi Singh, Brajesh K. Kaushik, Sudeb Dasgupta
    Pages 146-152

  20. Impact of Fin Width and Graded Channel Doping on the Performance of 22nm SOI FinFET

    • Jose Joseph, Rajendra Patrikar
    Pages 153-159
Back to top

Keywords

About this book

This book constitutes the refereed proceedings of the 17th International Symposium on VLSI Design and Test, VDAT 2013, held in Jaipur, India, in July 2013. The 44 papers presented were carefully reviewed and selected from 162 submissions. The papers discuss the frontiers of design and test of VLSI components, circuits and systems. They are organized in topical sections on VLSI design, testing and verification, embedded systems, emerging technology.

Editors and Affiliations

  • MNIT, Jaipur, India

    Manoj Singh Gaur, Vijay Laxmi, Dharmendra Boolchandani

  • University of Southampton, UK

    Mark Zwolinski

  • IIT Bombay, Mumbai, India

    Virendra Sing

  • Auburn University, USA

    Adit D. Sing

Bibliographic Information

  • Book Title: VLSI Design and Test

  • Book Subtitle: 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Proceedings

  • Editors: Manoj Singh Gaur, Mark Zwolinski, Vijay Laxmi, Dharmendra Boolchandani, Virendra Sing, Adit D. Sing

  • Series Title: Communications in Computer and Information Science

  • DOI: https://doi.org/10.1007/978-3-642-42024-5

  • Publisher: Springer Berlin, Heidelberg

  • eBook Packages: Computer Science, Computer Science (R0)

  • Copyright Information: Springer-Verlag Berlin Heidelberg 2013

  • Softcover ISBN: 978-3-642-42023-8Published: 10 December 2013

  • eBook ISBN: 978-3-642-42024-5Published: 13 December 2013

  • Series ISSN: 1865-0929

  • Series E-ISSN: 1865-0937

  • Edition Number: 1

  • Number of Pages: XVI, 388

  • Number of Illustrations: 246 b/w illustrations

  • Topics: Computer Hardware, Processor Architectures, Computer Communication Networks

Publish with us

Policies and ethics

Back to top

Search

Navigation