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Computer Science - Hardware | Transactions on High-Performance Embedded Architectures and Compilers III

Transactions on High-Performance Embedded Architectures and Compilers III

Stenström, Per (Ed.)

2011, XIV, 299p.

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Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This third issue contains 14 papers carefully reviewed and selected out of numerous submissions and is divided into four sections. The first section contains the top four papers from the Third International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, in January 2008. The second section consists of four papers from the 8th MEDEA Workshop held in conjunction with PACT 2007 in Brasov, Romania, in September 2007. The third section  contains two regular papers and the fourth section provides a snapshot from the First Workshop on Programmability Issues for Multicore Computers, MULTIPROG, held in conjunction with HiPEAC 2008.

Content Level » Research

Keywords » application specific systems - dynamic cache partitioning - dynamic compilation - embedded computing - embedded systems - high performance computing - memory hierarchies - memory systems - multicore systems - parallelization - power-aware systems design - processor architectures - program analysis - program optimization - reconfigurable architectures - supercomputing - transactional memory - virtual machine

Related subjects » Communication Networks - Hardware - Software Engineering

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