Walter, Colin D., Koc, Cetin K., Paar, Christof (Eds.)
2003, XIV, 446 p.
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These are the proceedings of CHES 2003, the ?fth workshop on Cryptographic HardwareandEmbeddedSystems,heldinCologneonSeptember8–10,2003.As with every previous workshop, there was a record number of submissions despite themuchearlierdeadlineinthisyear’scallforpapers.Thisisaclearindication of the growing international importance of the scope of the conference and the relevance of the subject material to both industry and academia. The increasing competition for presenting at the conference has led to many excellent papers and a higher standard overall. From the 111 submissions, time constraintsmeantthatonly32couldbeaccepted.Theprogramcommitteewo- ed very hard to select the best. However, at the end of the review process there were a number of good papers – which it would like to have included but for which, sadly, there was insu?cient space. In addition to the accepted papers appearing in this volume, there were three invited presentations from Hans D- bertin (Ruhr-Universit¨ at Bochum, Germany), Adi Shamir (Weizmann Institute, Israel), and Frank Stajano (University of Cambridge, UK), and a panel d- cussion on the e?ectiveness of current hardware and software countermeasures against side channel leakage in embedded cryptosystems.
Invited Talk.- The Security Challenges of Ubiquitous Computing.- Side Channel Attack Methodology.- Multi-channel Attacks.- Hidden Markov Model Cryptanalysis.- Power-Analysis Attacks on an FPGA – First Experimental Results.- Hardware Factorization.- Hardware to Solve Sparse Systems of Linear Equations over GF(2).- Symmetric Ciphers: Side Channel Attacks and Countermeasures.- Cryptanalysis of DES Implemented on Computers with Cache.- A Differential Fault Attack Technique against SPN Structures, with Application to the AES and Khazad.- A New Algorithm for Switching from Arithmetic to Boolean Masking.- DeKaRT: A New Paradigm for Key-Dependent Reversible Circuits.- Secure Hardware Logic.- Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers.- Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology.- Security Evaluation of Asynchronous Circuits.- Random Number Generators.- Design and Implementation of a True Random Number Generator Based on Digital Circuit Artifacts.- True Random Number Generators Secure in a Changing Environment.- How to Predict the Output of a Hardware Random Number Generator.- Efficient Multiplication.- On Low Complexity Bit Parallel Polynomial Basis Multipliers.- Efficient Modular Reduction Algorithm in [x] and Its Application to “Left to Right” Modular Multiplication in [x].- Faster Double-Size Modular Multiplication from Euclidean Multipliers.- More on Efficient Arithmetic.- Efficient Exponentiation for a Class of Finite Fields GF(2 n ) Determined by Gauss Periods.- GCD-Free Algorithms for Computing Modular Inverses.- Attacks on Asymmetric Cryptosystems.- Attacking Unbalanced RSA-CRT Using SPA.- The Doubling Attack – Why Upwards Is Better than Downwards.- An Analysis of Goubin’s Refined Power Analysis Attack.- A New Type of Timing Attack: Application to GPS.- Implementation of Symmetric Ciphers.- Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia.- Very Compact FPGA Implementation of the AES Algorithm.- Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs.- Hyperelliptic Curve Cryptography.- Hyperelliptic Curve Cryptosystems: Closing the Performance Gap to Elliptic Curves.- Countermeasures against Differential Power Analysis for Hyperelliptic Curve Cryptosystems.- Countermeasures to Side Channel Leakage.- A Practical Countermeasure against Address-Bit Differential Power Analysis.- A More Flexible Countermeasure against Side Channel Attacks Using Window Method.- Security of Standards.- On the Security of PKCS #11.- Attacking RSA-Based Sessions in SSL/TLS.