Network-on-Chip Architectures

1. Front Matter

   Pages i-xxi

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2. MICRO-Architectural Exploration

   1. Front Matter

      Pages 18-18

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   2. Introduction

      • Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

      Pages 1-12

   3. A Baseline NoC Architecture

      • Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

      Pages 13-16

   4. ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39]

      • Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

      Pages 19-40

   5. RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40]

      • Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

      Pages 41-64

   6. Exploring FaultoTolerant Network-on-Chip Architectures [37]

      • Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

      Pages 65-92

   7. On the Effects of Process Variation in Network-on-Chip Architectures [45]

      • Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

      Pages 93-115

3. MACRO-Architectural Exploration

   1. Front Matter

      Pages 118-118

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   2. The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15]

      • Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

      Pages 119-146

   3. Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43]

      • Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

      Pages 147-170

   4. A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44]

      • Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

      Pages 171-197

   5. Digest of Additional NoC MACRO-Architectural Research

      • Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

      Pages 199-205

   6. Conclusions and Future Work

      • Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das

      Pages 207-209

4. Back Matter

   Pages 211-223

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[2]. The Cell Processor from Sony, Toshiba and IBM (STI) [3], and the Sun UltraSPARC T1 (formerly codenamed Niagara) [4] signal the growing popularity of such systems. Furthermore, Intel’s very recently announced 80-core TeraFLOP chip [5] exemplifies the irreversible march toward many-core systems with tens or even hundreds of processing elements. 1.2 The Dawn of the Communication-Centric Revolution The multi-core thrust has ushered the gradual displacement of the computati- centric design model by a more communication-centric approach [6]. The large, sophisticated monolithic modules are giving way to several smaller, simpler p- cessing elements working in tandem. This trend has led to a surge in the popularity of multi-core systems, which typically manifest themselves in two distinct incarnations: heterogeneous Multi-Processor Systems-on-Chip (MPSoC) and homogeneous Chip Multi-Processors (CMP). The SoC philosophy revolves around the technique of Platform-Based Design (PBD) [7], which advocates the reuse of Intellectual Property (IP) cores in flexible design templates that can be customized accordingly to satisfy the demands of particular implementations. The appeal of such a modular approach lies in the substantially reduced Time-To- Market (TTM) incubation period, which is a direct outcome of lower circuit complexity and reduced design effort. The whole system can now be viewed as a diverse collection of pre-existing IP components integrated on a single die.

• Computer Architecture
• Energy Efficiency
• Fault Tolerance
• Network-on-Chip
• On-Chip Interconnects
• integrated circuit
• network on chip (NoC)
• processor
• reliability
• transistor

• Dept. Electrical & Computer Engineering, University of Cyprus, Nicosia, Cyprus

  Chrysostomos Nicopoulos

• Dept. Computer Science & Engineering, Pennsylvania State University, University Park, U.S.A.

  Vijaykrishnan Narayanan, Chita R. Das

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