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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers

  • Conference proceedings
  • © 2013

Overview

Editors:
  1. José L. Ayala

    1. Facultad de Informática, Complutense University of Madrid, Madrid, Spain

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  2. Delong Shang

    1. School of Electronic Engineering, Newcastle University, Newcastle upon Tyne, England, UK

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  3. Alex Yakovlev

    1. School of Electronic Engineering, Newcastle University, Newcastle upon Tyne, England, UK

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 7606)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

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Conference proceedings info: PATMOS 2012.

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Table of contents (25 papers)

  1. Front Matter

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  2. Sleep-Transistor Based Power-Gating Tradeoff Analyses

    • Sven Rosinger, Wolfgang Nebel
    Pages 1-10

  3. Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level

    • Chenxi Ni, Ziyad Al Tarawneh, Gordon Russell, Alex Bystrov
    Pages 11-20

  4. Non-invasive Power Simulation at System-Level with SystemC

    • Daniel Lorenz, Philipp A. Hartmann, Kim Grüttner, Wolfgang Nebel
    Pages 21-31

  5. A Standard Cell Optimization Method for Near-Threshold Voltage Operations

    • Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera
    Pages 32-41

  6. An Extended Metastability Simulation Method for Synchronizer Characterization

    • Salomon Beer, Ran Ginosar
    Pages 42-51

  7. Phase Space Based NBTI Model

    • Reef Eilers, Malte Metzdorf, Sven Rosinger, Domenik Helms, Wolfgang Nebel
    Pages 52-61

  8. Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths

    • Axel Reimer, Lars Kosmann, Daniel Lorenz, Wolfgang Nebel
    Pages 62-71

  9. Noise Margin Based Library Optimization Considering Variability in Sub-threshold

    • Tobias Gemmeke, Maryam Ashouei, Tobias G. Noll
    Pages 72-82

  10. TCP Window Based DVFS for Low Power Network Controller SoC

    • Eyal-Itzhak Nave, Ran Ginosar
    Pages 83-92

  11. Adaptive Synchronization for DVFS Applications

    • Ghaith Tarawneh, Alex Yakovlev
    Pages 93-102

  12. Muller C-Element Metastability Containment

    • Thomas Polzer, Andreas Steininger, Jakob Lechner
    Pages 103-112

  13. Low Power Implementation of Trivium Stream Cipher

    • J. M. Mora-Gutiérrez, C. J. Jiménez-Fernández, M. Valencia-Barrero
    Pages 113-120

  14. A Generic Architecture for Robust Asynchronous Communication Links

    • Jakob Lechner, Robert Najvirt
    Pages 121-130

  15. Direct Statistical Simulation of Timing Properties in Sequential Circuits

    • Javier Rodríguez, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs
    Pages 131-141

  16. PVTA Tolerant Self-adaptive Clock Generation Architecture

    • Jordi Pérez-Puigdemont, Antonio Calomarde, Francesc Moll
    Pages 142-154

  17. On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture

    • Hossein Karimiyan Alidash, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
    Pages 155-165

  18. Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications

    • Juan Núñez, María J. Avedillo, José M. Quintana
    Pages 166-174

  19. Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor

    • Pieter Weckx, Nele Reynders, Ilse de Moffarts, Wim Dehaene
    Pages 175-184

  20. Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation

    • Dimitris Bekiaris, Ioannis Kosmadakis, George Stassinopoulos, Dimitrios Soudris, Theodoros Laopoulos, Gregory Doumenis et al.
    Pages 185-193
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Other volumes

  1. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

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About this book

This book constitutes the refereed proceedings of the 22nd International Conference on Integrated Circuit and System Design, PATMOS 2012, held in Newcastle, UK Spain, in September 2012. The 25 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGAs. The technical program focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.

Editors and Affiliations

  • Facultad de Informática, Complutense University of Madrid, Madrid, Spain

    José L. Ayala

  • School of Electronic Engineering, Newcastle University, Newcastle upon Tyne, England, UK

    Delong Shang, Alex Yakovlev

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