Architecture of Computing Systems - ARCS 2011

1. Front Matter

   PDF

2. Customization and Application Specific Accelerators

   1. A Code-Based Analytical Approach for Using Separate Device Coprocessors in Computing Systems

      • Volker Hampel, Grigori Goronzy, Erik Maehle

      Pages 1-12

   2. Scalability Evaluation of a Polymorphic Register File: A CG Case Study

      • Cătălin B. Ciobanu, Xavier Martorell, Georgi K. Kuzmanov, Alex Ramirez, Georgi N. Gaydadjiev

      Pages 13-25

   3. Experiences with String Matching on the Fermi Architecture

      • Antonino Tumeo, Simone Secchi, Oreste Villa

      Pages 26-37

3. Multi/Many-Core Architectures

   1. Using Amdahl’s Law for Performance Analysis of Many-Core SoC Architectures Based on Functionally Asymmetric Processors

      • Hao Shen, Frédéric Pétrot

      Pages 38-49

   2. Application-Aware Power Saving for Online Transaction Processing Using Dynamic Voltage and Frequency Scaling in a Multicore Environment

      • Yuto Hayamizu, Kazuo Goda, Miyuki Nakano, Masaru Kitsuregawa

      Pages 50-61

   3. Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration

      • Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert

      Pages 62-73

4. Adaptive System Architectures

   1. Emulating Transactional Memory on FPGA Multiprocessors

      • Matteo Pusceddu, Simone Ceccolini, Antonino Tumeo, Gianluca Palermo, Donatella Sciuto

      Pages 74-85

   2. Architecture of an Adaptive Test System Built on FPGAs

      • Jörg Sachße, Heinz-Dietrich Wuttke, Steffen Ostendorff, Jorge H. Meza Escobar

      Pages 86-97

   3. An Extensible Framework for Context-Aware Smart Environments

      • Angham A. Sabagh, Adil Al-Yasiri

      Pages 98-109

5. Processor Architectures

   1. Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3

      • Jaroslav Sykora, Leos Kafka, Martin Danek, Lukas Kohout

      Pages 110-121

   2. A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardware

      • Stefan Metzlaff, Irakli Guliashvili, Sascha Uhrig, Theo Ungerer

      Pages 122-134

   3. Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy

      • Marius Grannaes, Magnus Jahre, Lasse Natvig

      Pages 135-146

6. Memory Architectures Optimisation

   1. Compiler-Assisted Selection of a Software Transactional Memory System

      • Martin Schindewolf, Alexander Esselson, Wolfgang Karl

      Pages 147-157

   2. An Instruction to Accelerate Software Caches

      • Arnaldo Azevedo, Ben Juurlink

      Pages 158-170

   3. Memory-, Bandwidth-, and Power-Aware Multi-core for a Graph Database Workload

      • Pedro Trancoso, Norbert Martinez, Josep-Lluis Larriba-Pey

      Pages 171-182

7. Organic and Autonomic Computing

   1. A Light-Weight Approach for Online State Classification of Self-organizing Parallel Systems

      • David Kramer, Rainer Buchty, Wolfgang Karl

      Pages 183-194

   2. Towards Organic Active Vision Systems for Visual Surveillance

      • Michael Wittke, Carsten Grenz, Jörg Hähner

      Pages 195-206

   3. Emergent Behaviour in Collaborative Indoor Localisation: An Example of Self-organisation in Ubiquitous Sensing Systems

      • Kamil Kloch, Gerald Pirkl, Paul Lukowicz, Carl Fischer

      Pages 207-218

8. Network-on-Chip Architectures

   1. An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel Allocation

      • Son Truong Nguyen, Shigeru Oyanagi

      Pages 219-230

This book constitutes the refereed proceedings of the 24th International Conference on Architecture of Computing Systems, ARCS 2011, held in Lake Como, Italy, in February 2011. The 22 revised full papers presented in seven technical sessions were carefully reviewed and selected from 62 submissions. The papers are organized in topical sections on customization and application specific accelerators; multi/many-core architectures; adaptive system architectures; processor architectures; memory architectures optimization; organic and autonomic computing; network-on-chip architectures.

• FPGA
• embedded systems
• energy-aware architectures
• operating systems
• pervasive computing
• power-aware systems
• reconfigurable systems
• self-organizing systems
• system-on-chip architectures
• transaction processing
• transactional memory systems
• ubiquitous computing

• Institut für Datentechnik und Kommunikationsnetze, Braunschweig, Germany

  Mladen Berekovic

• Dipartimento di elettronica e informazione, Milano, Italy

  William Fornaciari, Cristina Silvano

• Johann Wolfgang Goethe-Universität Frankfurt, Frankfurt am Main, Germany

  Uwe Brinkschulte

Policies and ethics