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High Performance Embedded Architectures and Compilers

5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings

  • Conference proceedings
  • © 2010

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Editors:
  1. Yale N. Patt

    1. Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, USA

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  2. Pierfrancesco Foglia

    1. Dipartimento di Ingegneria della Informazione, Università di Pisa, Pisa, Italy

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  3. Evelyn Duesterwald

    1. IBM T.J.Watson Research Center, Hawthorne, USA

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  4. Paolo Faraboschi

    1. Hewlett-Packard, Cami de Can Graells 1-21, Sant Cugat del Vallés, Barcelona, Spain

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  5. Xavier Martorell

    1. Computer Architecture Department, Technical University of Catalunya (UPC), Barcelona, Spain

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 5952)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: HiPEAC 2010.

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Table of contents (26 papers)

  1. Front Matter

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  2. Invited Program

    1. Embedded Systems as Datacenters

      • Bob Iannucci
      Pages 1-1

    2. Larrabee: A Many-Core Intel Architecture for Visual Computing

      • Roger Espasa
      Pages 2-2

  3. Architectural Support for Concurrency

    1. Remote Store Programming

      • Henry Hoffmann, David Wentzlaff, Anant Agarwal
      Pages 3-17

    2. Low-Overhead, High-Speed Multi-core Barrier Synchronization

      • John Sartori, Rakesh Kumar
      Pages 18-34

    3. Improving Performance by Reducing Aborts in Hardware Transactional Memory

      • Mohammad Ansari, Behram Khan, Mikel Luján, Christos Kotselidis, Chris Kirkham, Ian Watson
      Pages 35-49

    4. Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems

      • Cesare Ferri, Samantha Wood, Tali Moreshet, Iris Bahar, Maurice Herlihy
      Pages 50-65

  4. Compilation and Runtime Systems

    1. Split Register Allocation: Linear Complexity Without the Performance Penalty

      • Boubacar Diouf, Albert Cohen, Fabrice Rastello, John Cavazos
      Pages 66-80

    2. Trace-Based Data Layout Optimizations for Multi-core Processors

      • Olga Golovanevsky, Alon Dayan, Ayal Zaks, David Edelsohn
      Pages 81-95

    3. Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors

      • Paul M. Carpenter, Alex Ramirez, Eduard Ayguadé
      Pages 96-110

    4. Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures

      • Alexander Monakov, Anton Lokhmotov, Arutyun Avetisyan
      Pages 111-125

  5. Reconfigurable and Customized Architectures

    1. Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions

      • Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne
      Pages 126-140

    2. Accelerating XML Query Matching through Custom Stack Generation on FPGAs

      • Roger Moussalli, Mariam Salloum, Walid Najjar, Vassilis Tsotras
      Pages 141-155

    3. An Application-Aware Load Balancing Strategy for Network Processors

      • Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf
      Pages 156-170

    4. Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays

      • Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee Yoon, Yunheung Paek
      Pages 171-185

  6. Multicore Efficiency, Reliability, and Power

    1. Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors

      • Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott Mahlke
      Pages 186-200

    2. Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors

      • Yunlian Jiang, Kai Tian, Xipeng Shen
      Pages 201-215

    3. RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor

      • Houman Homayoun, Aseem Gupta, Alex Veidenbaum, Avesta Sasan (M.A. Makhzan), Fadi Kurdahi, Nikil Dutt
      Pages 216-231

    4. Performance and Power Aware CMP Thread Allocation Modeling

      • Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny
      Pages 232-246

  7. Memory Organization and Optimization

    1. Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching

      • Marius Grannaes, Magnus Jahre, Lasse Natvig
      Pages 247-261
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  1. High Performance Embedded Architectures and Compilers

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About this book

This book constitutes the refereed proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010. The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were carefully reviewed and selected from 94 submissions. The papers are organized in topical sections on architectural support for concurrency; compilation and runtime systems; reconfigurable and customized architectures; multicore efficiency, reliability, and power; memory organization and optimization; and programming and analysis of accelerators.

Editors and Affiliations

  • Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, USA

    Yale N. Patt

  • Dipartimento di Ingegneria della Informazione, Università di Pisa, Pisa, Italy

    Pierfrancesco Foglia

  • IBM T.J.Watson Research Center, Hawthorne, USA

    Evelyn Duesterwald

  • Hewlett-Packard, Cami de Can Graells 1-21, Sant Cugat del Vallés, Barcelona, Spain

    Paolo Faraboschi

  • Computer Architecture Department, Technical University of Catalunya (UPC), Barcelona, Spain

    Xavier Martorell

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