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Cryptographic Hardware and Embedded Systems - CHES 2007

9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings

  • Conference proceedings
  • © 2007
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Editors:
  1. Pascal Paillier
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    You can also search for this editor in PubMed   Google Scholar

  2. Ingrid Verbauwhede
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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 4727)

Part of the book sub series: Security and Cryptology (LNSC)

Included in the following conference series:

Conference proceedings info: CHES 2007.

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Table of contents (32 papers)

  1. Front Matter

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  2. Differential and Higher Order Attacks

    1. A First-Order DPA Attack Against AES in Counter Mode with Unknown Initial Counter

      • Josh Jaffe
      Pages 1-13
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    2. Gaussian Mixture Models for Higher-Order Side Channel Analysis

      • Kerstin Lemke-Rust, Christof Paar
      Pages 14-27
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    3. Side Channel Cryptanalysis of a Higher Order Masking Scheme

      • Jean-Sébastien Coron, Emmanuel Prouff, Matthieu Rivain
      Pages 28-44
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  3. Random Number Generation and Device Identification

    1. High-Speed True Random Number Generation with Logic Gates Only

      • Markus Dichtl, Jovan Dj. Golić
      Pages 45-62
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    2. FPGA Intrinsic PUFs and Their Use for IP Protection

      • Jorge Guajardo, Sandeep S. Kumar, Geert-Jan Schrijen, Pim Tuyls
      Pages 63-80
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  4. Logic Styles: Masking and Routing

    1. Evaluation of the Masked Logic Style MDPL on a Prototype Chip

      • Thomas Popp, Mario Kirschbaum, Thomas Zefferer, Stefan Mangard
      Pages 81-94
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    2. Masking and Dual-Rail Logic Don’t Add Up

      • Patrick Schaumont, Kris Tiri
      Pages 95-106
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    3. DPA-Resistance Without Routing Constraints?

      • Benedikt Gierlichs
      Pages 107-120
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  5. Efficient Algorithms for Embedded Processors

    1. On the Power of Bitslice Implementation on Intel Core2 Processor

      • Mitsuru Matsui, Junko Nakajima
      Pages 121-134
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    2. Highly Regular Right-to-Left Algorithms for Scalar Multiplication

      • Marc Joye
      Pages 135-147
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    3. MAME: A Compression Function with Reduced Hardware Requirements

      • Hirotaka Yoshida, Dai Watanabe, Katsuyuki Okeya, Jun Kitahara, Hongjun Wu, Özgül Küçük et al.
      Pages 148-165
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  6. Collision Attacks and Fault Analysis

    1. Collision Attacks on AES-Based MAC: Alpha-MAC

      • Alex Biryukov, Andrey Bogdanov, Dmitry Khovratovich, Timo Kasper
      Pages 166-180
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    2. Secret External Encodings Do Not Prevent Transient Fault Analysis

      • Christophe Clavier
      Pages 181-194
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    3. Two New Techniques of Side-Channel Cryptanalysis

      • Alex Biryukov, Dmitry Khovratovich
      Pages 195-208
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  7. High Speed AES Implementations

    1. AES Encryption Implementation and Analysis on Commodity Graphics Processing Units

      • Owen Harrison, John Waldron
      Pages 209-226
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    2. Multi-gigabit GCM-AES Architecture Optimized for FPGAs

      • Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert Felber, Matthias Braendli
      Pages 227-238
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  8. Public-Key Cryptography

    1. Arithmetic Operators for Pairing-Based Cryptography

      • Jean-Luc Beuchat, Nicolas Brisebarre, Jérémie Detrey, Eiji Okamoto
      Pages 239-255
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    2. FPGA Design of Self-certified Signature Verification on Koblitz Curves

      • Kimmo Järvinen, Juha Forsten, Jorma Skyttä
      Pages 256-271
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    3. How to Maximize the Potential of FPGA Resources for Modular Exponentiation

      • Daisuke Suzuki
      Pages 272-288
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  1. Cryptographic Hardware and Embedded Systems - CHES 2007

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About this book

CHES2007,theninthworkshoponCryptographicHardwareandEmbeddedS- tems, was sponsored by the International Association for Cryptologic Research (IACR) and held in Vienna, Austria, September 10–13, 2007. The workshop - ceived 99 submissions from 24 countries, of which the Program Committee (39 members from 15 countries) selected 31 for presentation. For the ?rst time in the history of CHES, each submission was reviewed by at least four reviewers instead of three (and at least ?ve for submissions by PC members, those now being limited to two per member) and many submitted papers have received plenty of extra reviews (some papers received up to nine reviews), thus totalling the unprecedented record of 483 reviews overall. Thepaperscollectedinthisvolumerepresentcutting-edgeworldwideresearch in the rapidly evolving ?elds of crypto-hardware, fault-based and side-channel cryptanalysis, and embedded cryptography, at the crossing of academic and - dustrial research. The wide diversity of subjects appearing in these proceedings covers virtually all related areas and shows our e?orts to extend the scope of CHES more than usual. Although a relatively young workshop, CHES is now ?rmlyestablishedasascienti?ceventofreferenceappreciatedbymoreandmore renowned experts of theory and practice: many high-quality works were subm- ted, all of which, sadly, could not be accepted. Selecting from so many good worksis no easy task and our deepest thanks go to the members of the Program Committee for their involvement, excellence, and team spirit. We are grateful to the numerous external reviewers listed below for their expertise and assistance in our deliberations.

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