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Power-Aware Computer Systems

First International Workshop, PACS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers

  • Conference proceedings
  • © 2001

Overview

Editors:
  1. Babak Falsafi

    1. Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, USA

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  2. T. N. Vijaykumar

    1. School of Electrical and Computer Engineering, Purdue University, W.Lafayette, USA

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 2008)

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Table of contents (11 papers)

  1. Front Matter

    Pages I-X
    Download chapter PDF

  2. Power-Aware Microarchitectural/Circuit Techniques

    1. System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors

      • Flavius Gruian
      Pages 1-12

    2. Ramp Up/Down Functional Unit to Reduce Step Power

      • Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, Sam Nakagawa, Lei He
      Pages 13-24

    3. An Adaptive Issue Queue for Reduced Power at High Performance

      • Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter Cook, David Albonesi
      Pages 25-39

  3. Application/Compiler Optimizations

    1. Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform

      • P. Marchal, C. Wong, A. Prayati, N. Cossement, F. Catthoor, R. Lauwereins et al.
      Pages 40-50

    2. Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering

      • Jeongseon Euh, Wayne Burleson
      Pages 51-64

    3. Compiler-Directed Dynamic Frequency and Voltage Scheduling

      • Chung-Hsing Hsu, Ulrich Kremer, Michael Hsiao
      Pages 65-81

  4. Exploiting IPC/Memory Slack

    1. Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power

      • Stefanos Kaxiras, Zhigang Hu, Girija Narlikar, Rae McLellan
      Pages 82-96

    2. Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors

      • Roberto Maro, Yu Bai, R. Iris Bahar
      Pages 97-111

  5. Power/Performance Models and Tools

    1. TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator

      • Ashutosh Dhodapkar, Chee How Lim, George Cai, W. Robert Daasch
      Pages 112-125

    2. Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor

      • David Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose
      Pages 126-136

    3. A Comparison of Two Architectural Power Models

      • Soraya Ghiasi, Dirk Grunwald
      Pages 137-151

  6. Back Matter

    Pages 153-153
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Keywords

About this book

The phenomenal increases in computer system performance in recent years have been accompanied by a commensurate increase in power and energy dissipation. The latter has directly resulted in demand for expensive packaging and cooling technology, an increase in product cost, and a decrease in product reliability in all segments of the computing market. Moreover, the higher power/energy dissipation has signi cantly reduced battery life in portable systems. While - stem designers have traditionally relied on circuit-level techniques to reduce - wer/energy, there is a growing need to address power/energy dissipation at all levels of the computer system. We are pleased to welcome you to the proceedings of the Power-Aware C- puter Systems (PACS 2000) workshop. PACS 2000 was the rst workshop in its series and its aim was to bring together experts from academia and industry to address power-/energy-awareness at all levels of computer systems. In these p- ceedings, we bring you several excellent research contributions spanning a wide spectrum of areas in power-aware systems, from application all the way to c- pilers and microarchitecture, and to power/performance estimating models and tools. We have grouped the contributions into the following speci c categories: (1) power-aware microarchitectural/circuit techniques, (2) application/compiler power optimizations, (3) exploiting opportunity for power optimization in - struction scheduling and cache memories, and (4) power/performance models and tools.

Editors and Affiliations

  • Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, USA

    Babak Falsafi

  • School of Electrical and Computer Engineering, Purdue University, W.Lafayette, USA

    T. N. Vijaykumar

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