Field Programmable Logic and Applications

1. Front Matter

   Pages I-XXVI

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2. Technologies and Trends

   1. Reconfigurable Circuits Using Hybrid Hall Effect Devices

      • Steve Ferrera, Nicholas P. Carter

      Pages 1-10

   2. Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory

      • Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Robert Heikaus, Okan Erdogan et al.

      Pages 11-20

3. Communications Applications

   1. Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture

      • Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu

      Pages 21-30

   2. Symbol Timing Synchronization in FPGA-Based Software Radios: Application to DVB-S

      • Francisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-Terre

      Pages 31-40

4. High Level Design Tools 1

   1. An Algorithm Designer’s Workbench for Platform FPGAs

      • Sumit Mohanty, Viktor K. Prasanna

      Pages 41-50

   2. Prototyping for the Concurrent Development of an IEEE 802.11 Wireless LAN Chipset

      • Ludovico de Souza, Philip Ryan, Jason Crawford, Kevin Wong, Greg Zyner, Tom McDermott

      Pages 51-60

5. Reconfigurable Architectures

   1. ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

      • Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins

      Pages 61-70

   2. Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches

      • Eryk Laskowski, Marek Tudruj

      Pages 71-80

   3. Arbitrating Instructions in an ρμ-Coded CCM

      • Georgi Kuzmanov, Stamatis Vassiliadis

      Pages 81-90

6. Cryptographic Applications 1

   1. How Secure Are FPGAs in Cryptographic Applications?

      • Thomas Wollinger, Christof Paar

      Pages 91-100

   2. FPGA Implementations of the RC6 Block Cipher

      • Jean-Luc Beuchat

      Pages 101-110

   3. Very High Speed 17 Gbps SHACAL Encryption Architecture

      • Máire McLoone, J. V. McCanny

      Pages 111-120

7. Place and Route Tools

   1. Track Placement: Orchestrating Routing Structures to Maximize Routability

      • Katherine Compton, Scott Hauck

      Pages 121-130

   2. Quark Routing

      • Sean T. McCulloch, James P. Cohoon

      Pages 131-140

   3. Global Routing for Lookup-Table Based FPGAs Using Genetic Algorithms

      • Jorge Barreiros, Ernesto Costa

      Pages 141-150

8. Multi-context FPGAs

   1. Virtualizing Hardware with Multi-context Reconfigurable Arrays

      • Rolf Enzler, Christian Plessl, Marco Platzner

      Pages 151-160

   2. A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device

      • Hideharu Amano, Akiya Jouraku, Kenichiro Anjo

      Pages 161-170

   3. Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device

      • Toshiro Kitaoka, Hideharu Amano, Kenichiro Anjo

      Pages 171-180

9. Cryptographic Applications 2

   1. Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES

      • Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat

      Pages 181-193

This book contains the papers presented at the 13th International Workshop on Field Programmable Logic and Applications (FPL) held on September 1–3, 2003. The conference was hosted by the Institute for Systems and Computer Engineering-Research and Development of Lisbon (INESC-ID) and the Depa- ment of Electrical and Computer Engineering of the IST-Technical University of Lisbon, Portugal. The FPL series of conferences was founded in 1991 at Oxford University (UK), and has been held annually since: in Oxford (3 times), Vienna, Prague, Darmstadt,London,Tallinn,Glasgow,Villach,BelfastandMontpellier.Itbrings together academic researchers, industrial experts, users and newcomers in an - formal,welcomingatmospherethatencouragesproductiveexchangeofideasand knowledge between delegates. Exciting advances in ?eld programmable logic show no sign of slowing down. New grounds have been broken in architectures, design techniques, run-time - con?guration, and applications of ?eld programmable devices in several di?erent areas. Many of these innovations are reported in this volume. The size of FPL conferences has grown signi?cantly over the years. FPL in 2002 saw 214 papers submitted, representing an increase of 83% when compared to the year before. The interest and support for FPL in the programmable logic community continued this year with 216 papers submitted. The technical p- gram was assembled from 90 selected regular papers and 56 posters, resulting in this volume of proceedings. The program also included three invited plenary keynote presentations from LSI Logic, Xilinx and Cadence, and three industrial tutorials from Altera, Mentor Graphics and Dafca.

• Performance
• Processing
• SoC
• Text
• Video
• algorithms
• cryptographic implementations
• dynamic reconfiguration
• field-programmable logic
• image processing
• low-power systems
• programming
• reconfigurable architecture
• reconfigurable logic
• robot

• Department of Electrical and Electronic Engineering, Imperial College London, London, UK

  Peter Cheung

• Department of Electrical & Electronic Engineering, Imperial College London, London, UK

  George A. Constantinides

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