High Performance Embedded Architectures and Compilers

1. Front Matter

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2. Invited Program

   1. Front Matter

      Pages 1-1

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   2. Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications

      • Markus Levy

      Pages 3-4

   3. Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges

      • Per Stenström

      Pages 5-5

   4. Software Defined Radio – A High Performance Embedded Challenge

      • Hyunseok Lee, Yuan Lin, Yoav Harel, Mark Woh, Scott Mahlke, Trevor Mudge et al.

      Pages 6-26

3. I Analysis and Evaluation Techniques

   1. Front Matter

      Pages 27-27

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   2. A Practical Method for Quickly Evaluating Program Optimizations

      • Grigori Fursin, Albert Cohen, Michael O’Boyle, Olivier Temam

      Pages 29-46

   3. Efficient Sampling Startup for Sampled Processor Simulation

      • Michael Van Biesbrouck, Lieven Eeckhout, Brad Calder

      Pages 47-67

   4. Enhancing Network Processor Simulation Speed with Statistical Input Sampling

      • Jia Yu, Jun Yang, Shaojie Chen, Yan Luo, Laxmi Bhuyan

      Pages 68-83

4. II Novel Memory and Interconnect Architectures

   1. Front Matter

      Pages 85-85

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   2. Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems

      • Ke Ning, David Kaeli

      Pages 87-101

   3. Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation

      • Michael J. Geiger, Sally A. McKee, Gary S. Tyson

      Pages 102-115

   4. Streaming Sparse Matrix Compression/Decompression

      • David Moloney, Dermot Geraghty, Colm McSweeney, Ciaran McElroy

      Pages 116-129

   5. XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs

      • Gansha Wu, Xin Zhou, Guei-Yuan Lueh, Jesse Z Fang, Peng Guo, Jinzhan Peng et al.

      Pages 130-149

5. III Security Architecture

   1. Front Matter

      Pages 151-151

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   2. Memory-Centric Security Architecture

      • Weidong Shi, Chenghuai Lu, Hsien-Hsin S. Lee

      Pages 153-168

   3. A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management

      • Abdulhadi Shoufan, Sorin A. Huss, Murtuza Cutleriwala

      Pages 169-183

   4. Arc3D: A 3D Obfuscation Architecture

      • Mahadevan Gomathisankaran, Akhilesh Tyagi

      Pages 184-199

6. IV Novel Compiler and Runtime Techniques

   1. Front Matter

      Pages 201-201

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   2. Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations

      • Jinpyo Kim, Sreekumar V. Kodakara, Wei-Chung Hsu, David J. Lilja, Pen-Chung Yew

      Pages 203-217

As Chairmen of HiPEAC 2005, we have the pleasure of welcoming you to the proceedings of the ?rst international conference promoted by the HiPEAC N- work of Excellence. During the last year, HiPEAC has been building its clusters of researchers in computer architecture and advanced compiler techniques for embedded and high-performance computers. Recently, the Summer School has been the seed for a fruitful collaboration of renowned international faculty and young researchers from 23 countries with fresh new ideas. Now, the conference promises to be among the premier forums for discussion and debate on these research topics. Theprestigeofasymposiumismainlydeterminedbythequalityofitstech- cal program. This ?rst programlived up to our high expectations, thanks to the largenumber of strong submissions. The ProgramCommittee received a total of 84 submissions; only 17 were selected for presentation as full-length papers and another one as an invited paper. Each paper was rigorously reviewed by three ProgramCommittee members and at least one external referee. Many reviewers spent a great amount of e?ort to provide detailed feedback. In many cases, such feedback along with constructive shepherding resulted in dramatic improvement in the quality of accepted papers. The names of the Program Committee m- bers and the referees are listed in the proceedings. The net result of this team e?ort is that the symposium proceedings include outstanding contributions by authors from nine countries in three continents. In addition to paper presentations, this ?rst HiPEAC conference featured two keynotes delivered by prominent researchers from industry and academia.

• Compiler
• compiler techniques
• computer architecture
• dynamic compilation
• embedded systems
• high-performance architecture
• memory system organization
• network computing
• network processors
• parallel architectures
• performance evaluation
• processor architectures
• reconfigurable architectures
• secured computing
• security processors

• NC State University, USA

  Tom Conte

• UPC, Spain

  Nacho Navarro

• Center for Reliable and High-Performance Computing and Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign,  

  Wen-mei W. Hwu

• Barcelona Supercomputing Center-CNS, Spain

  Mateo Valero

• Department of Computer Science, University of Augsburg, Augsburg, Germany

  Theo Ungerer

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