Integrated Circuit and System Design

1. Front Matter

   PDF

2. Keynote Speech

   1. Connecting E-Dreams to Deep-Submicron Realities

      • Hugo De Man

      Pages 1-1

3. Invited Talks

   1. Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization

      • Nick Kanopoulos

      Pages 2-2

   2. Low-Voltage Embedded RAMs – Current Status and Future Trends

      • Kiyoo Itoh, Kenichi Osada, Takayuki Kawahara

      Pages 3-15

   3. Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing

      • Carlo Dallavalle

      Pages 16-16

4. Embedded Tutorials

   1. Leakage in CMOS Circuits – An Introduction

      • D. Helms, E. Schmidt, W. Nebel

      Pages 17-35

   2. The Certainty of Uncertainty: Randomness in Nanometer Design

      • Hongliang Chang, Haifeng Qian, Sachin S. Sapatnekar

      Pages 36-47

5. Session 1: Buses and Communication

   1. Crosstalk Cancellation for Realistic PCB Buses

      • Jihong Ren, Mark R. Greenstreet

      Pages 48-57

   2. A Low-Power Encoding Scheme for GigaByte Video Interfaces

      • Sabino Salerno, Enrico Macii, Massimo Poncino

      Pages 58-68

   3. Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures

      • Markus Tahedl, Hans-Jörg Pfleiderer

      Pages 69-78

   4. Perfect 3-Limited-Weight Code for Low Power I/O

      • Mircea R. Stan, Yan Zhang

      Pages 79-89

   5. A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses

      • Claudia Kretzschmar, Torsten Bitterlich, Dietmar Müller

      Pages 90-99

6. Session 2: Circuits and Devices (I)

   1. Performance Metric Based Optimization Protocol

      • X. Michel, A. Verle, P. Maurine, N. Azémard, D. Auvergne

      Pages 100-109

   2. Temperature Dependence in Low Power CMOS UDSM Process

      • B. Lasbouygues, R. Wilson, P. Maurine, N. Azémard, D. Auvergne

      Pages 110-118

   3. Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques

      • Mauro Olivieri, Mirko Scarana, Giuseppe Scotti, Alessandro Trifiletti

      Pages 119-128

   4. High Yield Standard Cell Libraries: Optimization and Modeling

      • Nicola Dragone, Michele Quarantelli, Massimo Bertoletti, Carlo Guardiani

      Pages 129-137

   5. A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits

      • Gabriella Trucco, Giorgio Boselli, Valentino Liberali

      Pages 138-147

7. Session 3: Low Power (I)

   1. Sleepy Stack Reduction of Leakage Power

      • Jun Cheol Park, Vincent J. Mooney III, Philipp Pfeiffenberger

      Pages 148-158

   2. A Cycle-Accurate Energy Estimator for CMOS Digital Circuits

      • Eunseok Song, Young-Kil Park, Soon Kwon, Soo-Ik Chae

      Pages 159-168

   3. Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures

      • Christian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine

      Pages 169-178

WelcometotheproceedingsofPATMOS2004,thefourteenthinaseriesofint- national workshops. PATMOS 2004 was organized by the University of Patras with technical co-sponsorship from the IEEE Circuits and Systems Society. Over the years, the PATMOS meeting has evolved into an important - ropean event, where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design. PATMOS provides a forum for researchers to discuss and investigate the emerging challenges in - sign methodologies and tools required to develop the upcoming generations of integrated circuits and systems. We realized this vision this year by providing a technical program that contained state-of-the-art technical contributions, a keynote speech, three invited talks and two embedded tutorials. The technical program focused on timing, performance and power consumption, as well as architectural aspects, with particular emphasis on modelling, design, charac- rization, analysis and optimization in the nanometer era. This year a record 152 contributions were received to be considered for p- sible presentation at PATMOS. Despite the choice for an intense three-day m- ting, only 51 lecture papers and 34 poster papers could be accommodated in the single-track technical program. The Technical Program Committee, with the - sistance of additional expert reviewers, selected the 85 papers to be presented at PATMOS and organized them into 13 technical sessions. As was the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were received per manuscript.

• CAD design tools
• SoC systems
• circuit design
• computer architecture
• computer systems design
• integrated circuit design
• low power design
• modeling
• optimization
• performance analysis
• power-efficient design
• processor architecture
• systems modeling
• systems performance

• Politecnico di Torino, Torino, Italy

  Enrico Macii

• Electrical and Computer Engineering Department, University of Patras, Greece

  Vassilis Paliouras

• Department of Electrical and Computer Engineering, University of Patras, Patras, Greece

  Odysseas Koufopavlou

Policies and ethics