Defect and Fault Tolerance in VLSI Systems

1. Front Matter

   Pages i-xii

   PDF

2. Yield Models for Defect-Tolerant Vlsi Circuits: A Review

   1. Yield Models for Defect-Tolerant VLSI Circuits: A Review

      • Israel Koren, Charles H. Stapper

      Pages 1-21

3. Wafer Scale Revisited

   1. Wafer Scale Revisited

      • Douglas L. Peltzer

      Pages 23-31

4. Models for Defects and Yield

   1. Defects, Faults and Semiconductor Device Yield

      • A. V. Ferris-Prabhu

      Pages 33-46

   2. On the Probability of Fault Occurrence

      • Sharad C. Seth, Vishwani D. Agrawal

      Pages 47-52

   3. A New Yield Formula for Fault-Tolerant Large-Area Devices

      • C. Thibeault, Y. Savaria, J.-L. Houle

      Pages 53-64

5. Defect-Tolerant Designs

   1. Defect Tolerant Interconnects for VLSI

      • Michael C. Howells, Robert Aitken, Vinod K. Agarwal

      Pages 65-76

   2. Combining Architecture and Algorithm for Yield Enhancement and Fault Tolerance

      • R. J. Cosentino, B. L. Johnson, J. J. Vaccaro

      Pages 77-84

   3. Design of a Fault-Tolerant DRAM with New On-Chip ECC

      • P. Mazumder

      Pages 85-92

6. Defect Monitoring and Yield Projection

   1. Measurement and Distribution of Faults on Defect Test Site Chips

      • Reinhard Glang

      Pages 93-104

   2. Process Development and Circuit Design Interactions in VLSI Yield Improvement

      • James J. Hammond, Brian Boerman, Fred W. Voltmer

      Pages 105-116

   3. Yield Projection Based on Electrical Fault Distribution and Critical Structure Analysis

      • P. Schvan, D. Y. Montuno, R. Hadaway

      Pages 117-127

   4. Yield Model for Yield Projection from Test Site

      • Steven Magdo

      Pages 129-137

7. Testing and Testable Designs

   1. Test Methods for Wafer-Scale Integration

      • Koichi Yamashita, Shinpei Hijiya, Gensuke Goto, Nobutake Matsumura

      Pages 139-148

   2. Fault Diagnosis of Linear Processor Arrays

      • Donald Fussell, Sampath Rangarajan, Miroslaw Malek

      Pages 149-160

   3. Fault Diagnosis of Array Processors with Uniformly Distributed Faults

      • Michal Cutler, Minghsien Wang, Stephen Y. H. Su

      Pages 161-170

8. Defect- and Fault-Tolerant Processors

   1. Designing for High Yield: The NS32532 Microprocessor

      • B. Maytal, A. Danor, V. Karpati, R. Nassrallah, Y. Sidi, E. Shihadeh

      Pages 171-177

   2. Defect Tolerance in a 16-Bit Microprocessor

      • Regis Leveugle, Mohammad Soueidan, Norbert Wehn

      Pages 179-190

   3. Design Techniques for a Self-Checking Self-Exercising Processor

      • Savio Chau, David Rennels

      Pages 191-202

   4. Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors

      • G. S. Sohi

      Pages 203-212

This book contains an edited selection of papers presented at the International Workshop on Defect and Fault Tolerance in VLSI Systems held October 6-7, 1988 in Springfield, Massachusetts. Our thanks go to all the contributors and especially the members of the program committee for the difficult and time-consuming work involved in selecting the papers that were presented in the workshop and reviewing the papers included in this book. Thanks are also due to the IEEE Computer Society (in particular, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the University of Massachusetts at Amherst for sponsoring the workshop, and to the National Science Foundation for supporting (under grant number MIP-8803418) the keynote address and the distribution of this book to all workshop attendees. The objective of the workshop was to bring t. ogether researchers and practition­ ers from both industry and academia in the field of defect tolerance and yield en­ ha. ncement in VLSI to discuss their mutual interests in defect-tolerant architectures and models for integrated circuit defects, faults, and yield. Progress in this area was slowed down by the proprietary nature of yield-related data, and by the lack of appropriate forums for disseminating such information. The goal of this workshop was therefore to provide a forum for a dialogue and exchange of views. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. K. Jain from the University of South Florida as general co-chairmen, is being organized.

• Area
• VLSI
• algorithms
• architecture
• architectures
• distribution
• field
• forum
• forums
• information
• integrated circuit
• object
• review
• selection
• society

• University of Massachusetts, Amherst, USA

  Israel Koren

Policies and ethics