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  • © 2002

Test Resource Partitioning for System-on-a-Chip

Part of the book series: Frontiers in Electronic Testing (FRET, volume 20)

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Table of contents (10 chapters)

  1. Front Matter

    Pages i-xii
  2. Introduction

    1. Front Matter

      Pages 1-1
    2. Test Resource Partitioning

      • Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 3-15
  3. TRP For Test Hardware Optimization

    1. Front Matter

      Pages 17-17
    2. Test Access Mechanism Optimization

      • Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 19-43
    3. Improved Test Bus Partitioning

      • Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 45-64
    4. Test Wrapper and TAM Co-Optimization

      • Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 65-93
  4. TRP For Testing Time Minimization

    1. Front Matter

      Pages 94-94
    2. Test Scheduling Using Mixed-Integer Linear Programming

      • Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 97-118
    3. Precedence-Based, Preemptive, and Power-Constrained Test Scheduling

      • Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 119-134
  5. TRP For Test Data Volume Reduction

    1. Front Matter

      Pages 135-135
    2. Test Data Compression Using Golomb Codes

      • Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 137-178
    3. Frequency-Directed Run-Length (FDR) Codes

      • Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 179-201
    4. TRP for Low-Power Scan Testing

      • Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 203-216
    5. Conclusion

      • Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra
      Pages 217-221
  6. Back Matter

    Pages 223-232

About this book

Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic.

SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols.

Test Resource Partitioning for System-on-a-Chip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume.

Test Resource Partitioning for System-on-a-Chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements.

Authors and Affiliations

  • Department of Electrical and Computer Enginering, Duke University, Durham, England

    Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra

Bibliographic Information

Buy it now

Buying options

eBook USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access