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SystemVerilog Assertions and Functional Coverage

Guide to Language, Methodology and Applications

  • Book
  • © 2014

Overview

Authors:
  1. Ashok B. Mehta

    1. Los Gatos, USA

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  • Covers both SystemVerilog Assertions and Sytem Verilog Functional Coverage language and methodologies
  • Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies
  • Explains each concept in an easy to understand, step-by-step fashion and applies it to a real example
  • Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book
  • Includes supplementary material: sn.pub/extras

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Table of contents (22 chapters)

  1. Front Matter

    Pages i-xxxiii
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  2. Introduction

    • Ashok B. Mehta
    Pages 1-8

  3. System Verilog Assertions

    • Ashok B. Mehta
    Pages 9-28

  4. Immediate Assertions

    • Ashok B. Mehta
    Pages 29-31

  5. Concurrent Assertions: Basics (Sequence, Property, Assert)

    • Ashok B. Mehta
    Pages 33-57

  6. Sampled Value Functions $rose, $fell

    • Ashok B. Mehta
    Pages 59-70

  7. Operators

    • Ashok B. Mehta
    Pages 71-121

  8. System Functions and Tasks

    • Ashok B. Mehta
    Pages 123-129

  9. Multiple Clocks

    • Ashok B. Mehta
    Pages 131-142

  10. Local Variables

    • Ashok B. Mehta
    Pages 143-152

  11. Recursive Property

    • Ashok B. Mehta
    Pages 153-157

  12. Detecting and Using Endpoint of a Sequence

    • Ashok B. Mehta
    Pages 159-166

  13. ‘expect’

    • Ashok B. Mehta
    Pages 167-168

  14. ‘assume’ and Formal (Static Functional ) Verification

    • Ashok B. Mehta
    Pages 169-170

  15. Other Important Topics

    • Ashok B. Mehta
    Pages 171-209

  16. Asynchronous Assertions !!!

    • Ashok B. Mehta
    Pages 211-214

  17. IEEE-1800-2009 Features

    • Ashok B. Mehta
    Pages 215-253

  18. SystemVerilog Assertions LABs

    • Ashok B. Mehta
    Pages 255-294

  19. System Verilog Assertions: LAB Answers

    • Ashok B. Mehta
    Pages 295-311

  20. Functional Coverage

    • Ashok B. Mehta
    Pages 313-318
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Keywords

About this book

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage.  Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’.  Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects.  Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug.

Authors and Affiliations

  • Los Gatos, USA

    Ashok B. Mehta

About the author

Ashok Mehta is a senior manager in TSMC's CPU/SoC Architecture and Methodology group working on System and 3DIC design projects. In the past, Ashok worked in engineering and management positions at DEC, Data General, Intel and AMCC. He has extensive experience in Design/Verification of complex SoC and Processor devices. He holds nine US patents on ESL and 3DIC designs. Ashok holds a MSEE from University of Missouri.

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