Overview
- Authors:
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Sudipta Kundu
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Synopsis, Inc., Hillsboro, USA
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Sorin Lerner
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, Dept of Computer Science and Engineering, University of California, San Diego, La Jolla, USA
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Rajesh K. Gupta
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, Dept of Computer Science and Engineering, University of California, San Diego, La Jolla, USA
- Offers industry practitioners already involved with high-level synthesis an invaluable reference to high-level verification
- Uses a combination of formal techniques to do scalable verification of system designs completely automatically
- Presents techniques that guarantee properties verified in the high-level design are preserved through the translation to low-level RTL
- Written by researchers in work in mainstream hardware and software design and includes results from both academia and industry
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Table of contents (9 chapters)
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Front Matter
Pages i-xiii
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- Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
Pages 1-9
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- Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
Pages 11-23
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- Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
Pages 25-35
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- Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
Pages 37-50
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- Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
Pages 51-66
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- Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
Pages 97-121
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- Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
Pages 147-150
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Back Matter
Pages 151-167
About this book
Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of system designs completely automatically. The verification techniques presented in this book include methods for verifying properties of high-level designs and methods for verifying that the translation from high-level design to a low-level Register Transfer Language (RTL) design preserves semantics. Used together, these techniques guarantee that properties verified in the high-level design are preserved through the translation to low-level RTL.
