Coupled Data Communication Techniques for High-Performance and Low-Power Computing

1. Front Matter

   Pages i-xvi

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2. Introduction

   1. Front Matter

      Pages 1-1

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   2. Introduction to Coupled Data Technologies

      • Ron Ho, Robert Drost

      Pages 3-10

3. Overview of 3D Technologies

   1. Front Matter

      Pages 12-12

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   2. Power delivery, signaling and cooling for 2D and 3D integrated systems

      • Muhannad Bakir, Gang Huang, Bing Dang

      Pages 13-48

4. Coupled Data Technologies

   1. Front Matter

      Pages 50-50

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   2. Capacitive Coupled Communication

      • David Hopkins, Alex Chow, Frankie Liu, Dinesh D. Patil, Hans Eberle

      Pages 51-77

   3. Inductive Coupled Communications

      • Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda

      Pages 79-125

   4. Use of AC Coupled Interconnect in Contactless Packaging

      • Paul Franzon

      Pages 127-153

5. Enabling Coupled Data Technologies

   1. Front Matter

      Pages 156-156

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   2. Aligning chips face-to-face for dense capacitive communication

      • John E. Cunningham, Ashok V. Krishnamoorthy, Ivan Shubin, James G. Mitchell, Xuezhe Zheng

      Pages 157-175

6. Extending Data Coupling Technologies

   1. Front Matter

      Pages 178-178

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7. Extending Data Coupling Technologies

   1. Delivering On-chip Bandwidth Off-chip and Out-of-box with Proximity and Optical Communication

      • Ashok V. Krishnamoorthy, Jon Lexau, Xuezhe Zheng, John E. Cunningham

      Pages 179-192

   2. AC Coupled Wireless Power Delivery

      • Makoto Takamiya, Kohei Onizuka, Takayasu Sakurai

      Pages 193-204

8. Back Matter

   Pages 205-206

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Wafer-scale integration has long been the dream of system designers. Instead of chopping a wafer into a few hundred or a few thousand chips, one would just connect the circuits on the entire wafer. What an enormous capability wafer-scale integration would offer: all those millions of circuits connected by high-speed on-chip wires. Unfortunately, the best known optical systems can provide suitably ?ne resolution only over an area much smaller than a whole wafer. There is no known way to pattern a whole wafer with transistors and wires small enough for modern circuits. Statistical defects present a ?rmer barrier to wafer-scale integration. Flaws appear regularly in integrated circuits; the larger the circuit area, the more probable there is a ?aw. If such ?aws were the result only of dust one might reduce their numbers, but ?aws are also the inevitable result of small scale. Each feature on a modern integrated circuit is carved out by only a small number of photons in the lithographic process. Each transistor gets its electrical properties from only a small number of impurity atoms in its tiny area. Inevitably, the quantized nature of light and the atomic nature of matter produce statistical variations in both the number of photons de?ning each tiny shape and the number of atoms providing the electrical behavior of tiny transistors. No known way exists to eliminate such statistical variation, nor may any be possible.

• Drost
• Signal
• chip packaging
• communication
• complexity
• coupled data communication
• high-performance
• integrated circuit
• integrated circuits
• interconnect
• low-power
• manufacturing
• modeling

• Sun Microsystems Laboratories, VLSI Research Group, Sun Microsystems, Inc., Menlo Park, USA

  Ron Ho, Robert Drost

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