Skip to main content

Principles of Verifiable RTL Design

A functional coding style supporting verification processes in Verilog

  • Book
  • © 2000

Overview

  • 2114 Accesses

This is a preview of subscription content, log in via an institution to check access.

Access this book

eBook USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (9 chapters)

Keywords

About this book

Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.
The intended audience for Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset.
Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.

Authors and Affiliations

  • Hewlett-Packard Company, USA

    Lionel Bening, Harry Foster

Bibliographic Information

  • Book Title: Principles of Verifiable RTL Design

  • Book Subtitle: A functional coding style supporting verification processes in Verilog

  • Authors: Lionel Bening, Harry Foster

  • DOI: https://doi.org/10.1007/b116517

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Springer Science+Business Media New York 2000

  • Softcover ISBN: 978-1-4757-7313-2Published: 12 April 2013

  • eBook ISBN: 978-0-306-47016-5Published: 08 May 2007

  • Edition Number: 1

  • Number of Pages: XVII, 253

  • Number of Illustrations: 19 b/w illustrations

  • Topics: Circuits and Systems, Computer Hardware, Computer-Aided Engineering (CAD, CAE) and Design, Electrical Engineering

Publish with us