Editors:
- Focuses on timing analysis and optimization techniques for circuits with level-sensitive memory elements
- Contains a linear programming formulation applicable to the timing analysis of large scale circuits
- Includes a delay insertion methodology that improves the efficiency of clock skew scheduling in level-sensitive circuits
- Provides an overview of circuit partitioning, placement, and synchronization methodologies that enables the implementation of high speed, low power circuits synchronized with ultra-modern resonant clocking technology
- Provides a framework for and results from implementing the described timing optimization algorithms in a parallel computing environment
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Table of contents (11 chapters)
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Front Matter
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Back Matter
About this book
Editors and Affiliations
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University of Pittsburgh Pittsburgh, USA
Ivan S. Kourtev
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Drexel University Philadelphia, USA
Baris Taskin
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University of Rochester Rochester, USA
Eby G. Friedman
Bibliographic Information
Book Title: Timing Optimization Through Clock Skew Scheduling
Editors: Ivan S. Kourtev, Baris Taskin, Eby G. Friedman
DOI: https://doi.org/10.1007/978-0-387-71056-3
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer-Verlag US 2009
Hardcover ISBN: 978-0-387-71055-6Published: 21 November 2008
Softcover ISBN: 978-1-4419-4377-4Published: 04 November 2010
eBook ISBN: 978-0-387-71056-3Published: 16 November 2008
Edition Number: 1
Number of Pages: XVI, 266
Topics: Circuits and Systems, Electrical Engineering, Computer-Aided Engineering (CAD, CAE) and Design, Electronics and Microelectronics, Instrumentation