Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

1. Front Matter

   Pages I-XXI

   PDF

2. Introduction

   • Manoj Sachdev, José Pineda de Gyvez

   Pages 1-22

3. Functional and Parametric Defect Models

   • Manoj Sachdev, José Pineda de Gyvez

   Pages 23-67

4. Digital CMOS Fault Modeling

   • Manoj Sachdev, José Pineda de Gyvez

   Pages 69-110

5. Defects in Logic Circuits and their Test Implications

   • Manoj Sachdev, José Pineda de Gyvez

   Pages 111-150

6. Testing Defects and Parametric Variations in RAMs

   • Manoj Sachdev, José Pineda de Gyvez

   Pages 151-223

7. Defect-Oriented Analog Testing

   • Manoj Sachdev, José Pineda de Gyvez

   Pages 225-287

8. Yield Engineering

   • Manoj Sachdev, José Pineda de Gyvez

   Pages 289-315

9. Conclusion

   • Manoj Sachdev, José Pineda de Gyvez

   Pages 317-324

10. Back Matter

    Pages 325-328

    PDF

Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.

• CMOS
• DSM
• DfM
• RAM
• SRAM
• VLSI
• defects
• integrated circuit
• logic
• testing
• yield

• University of Waterloo, Ontario, Canada

  Manoj Sachdev

• Philips Research Laboratories, Eindhoven University of Technology, Eindhoven, The Netherlands

  José Pineda de Gyvez

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