Authors:
- A wide coverage of digital phase lock loops including a new class called TDTL
- Theoretical and practical aspects of digital phase lock loops
- FPGA-based reconfigurable implementation of digital phase lock loop architectures
- Selected applications of digital phase lock loops
- Includes supplementary material: sn.pub/extras
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Table of contents (8 chapters)
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Front Matter
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Back Matter
About this book
Digital phase lock loops are critical components of many communication, signal processing and control systems. This exciting new book covers various types of digital phase lock loops. It presents a comprehensive coverage of a new class of digital phase lock loops called the time delay tanlock loop (TDTL). It also details a number of architectures that improve the performance of the TDTL through adaptive techniques that overcome the conflicting requirements of the locking rage and speed of acquisition. These requirements are of paramount importance in many applications including wireless communications, consumer electronics and others. Digital Phase Lock Loops then illustrates the process of converting the TDTL class of digital phase lock loops for implementation on an FPGA-based reconfigurable system. These devices are being utilized in software-defined radio, DSP-based designs and many other communication and electronic systems to implement complex high-speed algorithms. Their flexibility and reconfigurability facilitate rapid prototyping, on-the-fly upgradeability, and code reuse with minimum effort and complexity. The practical real-time results, of the various TDTL architectures, obtained from the reconfigurable implementations are compared with those obtained through simulations with MATLAB/Simulink. The material in this book will be valuable to researchers, graduate students, and practicing engineers.
Keywords
- Digital phase lock loops
- Digital phase lock loops applications
- Digital phase lock loops noise analysis
- FPGA
- FPGA-based Reconfigurable Systems
- Filter
- Frequency estimation
- Hilbert Transforms
- Switch
- Time Delay Digital Tanlock Loops
- communication
- complexity
- development
- digital signal processor
- system analysis
Authors and Affiliations
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Communications Engineering Department, Etisalat University College, UAE
Saleh R. Al-araji
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School of Electrical and Computer Engineering, RMIT University, Australia
Zahir M. Hussain
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Department of Electronic Engineering, Etisalat University College, UAE
Mahmoud A. Al-qutayri
About the authors
Prof. Al-Araji received the B.Sc., M.Sc., and Ph.D. degrees from the University of Wales Swansea, (UK), all in electrical engineering in 1968, 1969, and 1972 respectively. Since September 2002, Professor Al-Araji was appointed Professor and Head of Communications Engineering Department at Etisalat University College (Emirates Telecommunication Cooperation), Sharjah, UAE. Prior to that and for six years he was working at the Transmission Network Systems, Scientific-Atlanta, Atlanta, Georgia, USA as Senior Staff Electrical Engineer. During the academic year 1995/1996, Prof. Al-Araji was visiting professor at the Ohio State University, Columbus, Ohio, USA. He was visiting professor at King’s College, University of London, England, during the summers of 1988 and 1989. Prof. Al-Araji was professor and Department Head at the University of Baghdad, Iraq, and the University of Yarmouk, Jordan.
Prof. Al-Araji was awarded the British IERE Clerk Maxwell Premium for a paper published in 1976 and the Scientific-Atlanta award for outstanding achievement in the year 2000. He was an Iraqi National member of URSI Commissions C and D, and the ITU (CCIR Group 8). His research interests include synchronization techniques, communication signal processing, and CATV systems and networks. He has published over 50 papers in international Journals and Conferences and holds 6 US Patents and one International Patent. He is a reviewer to a number of international conferences and journals, and is involved in the organization of a number of international conferences in various capacities. Prof. Al-Araji is a senior member of the IEEE. His e-mail address is: alarajis@euc.ac.ae.
Bibliographic Information
Book Title: Digital Phase Lock Loops
Book Subtitle: Architectures and Applications
Authors: Saleh R. Al-araji, Zahir M. Hussain, Mahmoud A. Al-qutayri
DOI: https://doi.org/10.1007/978-0-387-32864-5
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer-Verlag US 2006
Hardcover ISBN: 978-0-387-32863-8Published: 19 October 2006
Softcover ISBN: 978-1-4419-4105-3Published: 29 October 2010
eBook ISBN: 978-0-387-32864-5Published: 29 April 2007
Edition Number: 1
Number of Pages: XVIII, 192
Topics: Circuits and Systems, Electrical Engineering, Signal, Image and Speech Processing, Communications Engineering, Networks, Electronics and Microelectronics, Instrumentation